[xilinx-xlnx:master 129/214] drivers/clk/clk-xlnx-clock-wizard-v.c:164:9: error: implicit declaration of function 'FIELD_GET'
kernel test robot
lkp at intel.com
Sun Oct 31 14:28:16 PDT 2021
tree: https://github.com/Xilinx/linux-xlnx master
head: 6cb480b208248d57a9906d801469d7ea8292df52
commit: c1e2db426dc728a5417024c9bd75c39ec81331d9 [129/214] clocking-wizard: Support higher frequency accuracy
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/Xilinx/linux-xlnx/commit/c1e2db426dc728a5417024c9bd75c39ec81331d9
git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
git fetch --no-tags xilinx-xlnx master
git checkout c1e2db426dc728a5417024c9bd75c39ec81331d9
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All errors (new ones prefixed by >>):
drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_recalc_rate_all':
>> drivers/clk/clk-xlnx-clock-wizard-v.c:164:9: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration]
164 | regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);
| ^~~~~~~~~
drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_get_divisors':
drivers/clk/clk-xlnx-clock-wizard-v.c:229:4: warning: this decimal constant is unsigned only in ISO C90
229 | if (vco_freq >= WZRD_VCO_MIN && vco_freq <= WZRD_VCO_MAX) {
| ^~
drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_dynamic_all_nolock':
>> drivers/clk/clk-xlnx-clock-wizard-v.c:276:12: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
276 | regval1 = FIELD_PREP(WZRD_DIVCLK_EDGE, edged);
| ^~~~~~~~~~
drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_recalc_rate':
drivers/clk/clk-xlnx-clock-wizard-v.c:342:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
342 | (void __iomem *)((u64)divider->base + divider->offset);
| ^
drivers/clk/clk-xlnx-clock-wizard-v.c:342:4: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
342 | (void __iomem *)((u64)divider->base + divider->offset);
| ^
drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_dynamic_reconfig':
drivers/clk/clk-xlnx-clock-wizard-v.c:375:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
375 | (void __iomem *)((u64)divider->base + divider->offset);
| ^
drivers/clk/clk-xlnx-clock-wizard-v.c:375:4: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
375 | (void __iomem *)((u64)divider->base + divider->offset);
| ^
cc1: some warnings being treated as errors
vim +/FIELD_GET +164 drivers/clk/clk-xlnx-clock-wizard-v.c
154
155 static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw,
156 unsigned long parent_rate)
157 {
158 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
159 u32 edged, div, div2, p5en, edge, prediv2, all, regl, regh, mult, reg;
160
161 edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1)) & WZRD_CLKFBOUT_EDGE);
162
163 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_2));
> 164 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);
165 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
166
167 mult = regl + regh + edge;
168 if (!mult)
169 mult = 1;
170
171 regl = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_4)) &
172 WZRD_CLKFBOUT_FRAC_EN;
173 if (regl) {
174 regl = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_3)) &
175 WZRD_CLKFBOUT_FRAC_MASK;
176 mult = mult * WZRD_FRAC_GRADIENT + regl;
177 parent_rate = DIV_ROUND_CLOSEST((parent_rate * mult), WZRD_FRAC_GRADIENT);
178 } else {
179 parent_rate = parent_rate * mult;
180 }
181
182 /* O Calculation */
183 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1));
184 edged = FIELD_GET(WZRD_CLKFBOUT_EDGE, reg);
185 p5en = FIELD_GET(WZRD_P5EN, reg);
186 prediv2 = FIELD_GET(WZRD_CLKOUT0_PREDIV2, reg);
187
188 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_2));
189 /* Low time */
190 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);
191 /* High time */
192 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
193 all = regh + regl + edged;
194 if (!all)
195 all = 1;
196
197 if (prediv2)
198 div2 = PREDIV2_MULT * all + p5en;
199 else
200 div2 = all;
201
202 /* D calculation */
203 edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(WZRD_DESKEW_2)) &
204 WZRD_DIVCLK_EDGE);
205 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_DIVCLK));
206 /* Low time */
207 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);
208 /* High time */
209 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
210 div = regl + regh + edged;
211 if (!div)
212 div = 1;
213
214 div = div * div2;
215 return divider_recalc_rate(hw, parent_rate, div, divider->table,
216 divider->flags, divider->width);
217 }
218
219 static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
220 unsigned long parent_rate)
221 {
222 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
223 u64 vco_freq, freq, diff;
224 u32 m, d, o;
225
226 for (m = WZRD_M_MIN; m <= WZRD_M_MAX; m++) {
227 for (d = WZRD_D_MIN; d <= WZRD_D_MAX; d++) {
228 vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d);
229 if (vco_freq >= WZRD_VCO_MIN && vco_freq <= WZRD_VCO_MAX) {
230 for (o = WZRD_O_MIN; o <= WZRD_O_MAX; o++) {
231 freq = DIV_ROUND_CLOSEST(vco_freq, o);
232 diff = abs(freq - rate);
233
234 if (diff < WZRD_MIN_ERR) {
235 divider->valuem = m;
236 divider->valued = d;
237 divider->valueo = o;
238 return 0;
239 }
240 }
241 }
242 }
243 }
244 return -EBUSY;
245 }
246
247 static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate,
248 unsigned long parent_rate)
249 {
250 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
251 u32 value, regh, edged, p5en, p5fedge, value2, m, regval, regval1;
252 int err;
253
254 err = clk_wzrd_get_divisors(hw, rate, parent_rate);
255 if (err)
256 return err;
257
258 writel(0, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_4));
259
260 m = divider->valuem;
261 edged = m % WZRD_DUTY_CYCLE;
262 regh = m / WZRD_DUTY_CYCLE;
263 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1));
264 regval1 |= WZRD_MULT_PREDIV2;
265 if (edged)
266 regval1 = regval1 | WZRD_CLKFBOUT_EDGE;
267 else
268 regval1 = regval1 & ~WZRD_CLKFBOUT_EDGE;
269 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1));
270 regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
271 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_2));
272
273 value2 = divider->valued;
274 edged = value2 % WZRD_DUTY_CYCLE;
275 regh = (value2 / WZRD_DUTY_CYCLE);
> 276 regval1 = FIELD_PREP(WZRD_DIVCLK_EDGE, edged);
277 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_DESKEW_2));
278 regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
279 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_DIVCLK));
280
281 value = divider->valueo;
282 regh = value / WZRD_O_DIV;
283 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1));
284 regval1 |= WZRD_CLKFBOUT_PREDIV2;
285 regval1 = regval1 & ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE);
286 if (value % WZRD_O_DIV > 1) {
287 edged = 1;
288 regval1 |= edged << WZRD_CLKFBOUT_H_SHIFT;
289 }
290 p5fedge = value % WZRD_DUTY_CYCLE;
291 p5en = value % WZRD_DUTY_CYCLE;
292
293 regval1 = regval1 | FIELD_PREP(WZRD_P5EN, p5en) | FIELD_PREP(WZRD_P5FEDGE, p5fedge);
294 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1));
295 regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
296 writel(regval, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_2));
297
298 /* Check status register */
299 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
300 value, value & WZRD_DR_LOCK_BIT_MASK,
301 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
302 if (err)
303 return err;
304
305 /* Initiate reconfiguration */
306 writel(WZRD_DR_BEGIN_DYNA_RECONF,
307 divider->base + WZRD_DR_INIT_REG_OFFSET);
308
309 /* Check status register */
310 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
311 value, value & WZRD_DR_LOCK_BIT_MASK,
312 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
313 }
314
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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