[RESEND v2 5/5] PCI: imx6: Add the compliance tests mode support

[Richard Zhu]

> -----Original Message-----
> From: Lucas Stach <l.stach at pengutronix.de>
> Sent: Saturday, October 16, 2021 2:29 AM
> To: Richard Zhu <hongxing.zhu at nxp.com>; bhelgaas at google.com;
> lorenzo.pieralisi at arm.com
> Cc: linux-pci at vger.kernel.org; dl-linux-imx <linux-imx at nxp.com>;
> linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> kernel at pengutronix.de
> Subject: Re: [RESEND v2 5/5] PCI: imx6: Add the compliance tests mode
> support
> 
> Am Freitag, dem 15.10.2021 um 14:05 +0800 schrieb Richard Zhu:
> > Refer to the system board signal Quality of PCIe archiecture PHY test
> > specification. Signal quality tests(for example: jitters,
> > differential eye opening and so on ) can be executed with devices in
> > the polling.compliance state.
> >
> > To let the device support polling.compliance stat, the clocks and
> > powers shouldn't be turned off when the probe of device driver is failed.
> >
> > Based on CLB(Compliance Load Board) Test Fixture and so on test
> > equipments, the PHY link would be down during the compliance tests.
> > Refer to this scenario, add the i.MX PCIe compliance tests mode enable
> > support, and keep the clocks and powers on, and finish the driver
> > probe without error return.
> >
> > Use the "pci_imx6.compliance=1" in kernel command line to enable the
> > compliance tests mode.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 32
> > ++++++++++++++++++++-------
> >  1 file changed, 24 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index d6a5d99ffa52..e861a516d517 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -143,6 +143,10 @@ struct imx6_pcie {
> >  #define PHY_RX_OVRD_IN_LO_RX_DATA_EN		BIT(5)
> >  #define PHY_RX_OVRD_IN_LO_RX_PLL_EN		BIT(3)
> >
> > +static bool imx6_pcie_cmp_mode;
> > +module_param_named(compliance, imx6_pcie_cmp_mode, bool, 0644);
> > +MODULE_PARM_DESC(compliance, "i.MX PCIe compliance test mode
> > +(1=compliance test mode enabled)");
> > +
> >  static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool
> > exp_val)  {
> >  	struct dw_pcie *pci = imx6_pcie->pci; @@ -812,10 +816,12 @@ static
> > int imx6_pcie_start_link(struct dw_pcie *pci)
> >  	 * started in Gen2 mode, there is a possibility the devices on the
> >  	 * bus will not be detected at all.  This happens with PCIe switches.
> >  	 */
> > -	tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > -	tmp &= ~PCI_EXP_LNKCAP_SLS;
> > -	tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
> > -	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
> > +	if (!imx6_pcie_cmp_mode) {
> > +		tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > +		tmp &= ~PCI_EXP_LNKCAP_SLS;
> > +		tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
> > +		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
> > +	}
> >
> >  	/* Start LTSSM. */
> >  	imx6_pcie_ltssm_enable(dev);
> > @@ -876,9 +882,12 @@ static int imx6_pcie_start_link(struct dw_pcie
> *pci)
> >  		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
> >  		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
> >  	imx6_pcie_reset_phy(imx6_pcie);
> 
> Is it correct to reset the PHY here when in compliance test mode?
[Richard Zhu] It doesn't matter. PHY reset just let the PHY enter into a dedicated stat after link is down.
This wouldn't impact the compliance tests mode later.

Best Regards
Richard Zhu

> 
> > -	imx6_pcie_clk_disable(imx6_pcie);
> > -	if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0)
> > -		regulator_disable(imx6_pcie->vpcie);
> > +	if (!imx6_pcie_cmp_mode) {
> > +		imx6_pcie_clk_disable(imx6_pcie);
> > +		if (imx6_pcie->vpcie
> > +		    && regulator_is_enabled(imx6_pcie->vpcie) > 0)
> > +			regulator_disable(imx6_pcie->vpcie);
> > +	}
> >  	return ret;
> >  }
> >
> > @@ -1183,8 +1192,15 @@ static int imx6_pcie_probe(struct
> platform_device *pdev)
> >  		return ret;
> >
> >  	ret = dw_pcie_host_init(&pci->pp);
> > -	if (ret < 0)
> > +	if (ret < 0) {
> > +		if (imx6_pcie_cmp_mode) {
> > +			dev_info(dev, "Driver loaded with compliance test mode
> enabled.\n");
> > +			ret = 0;
> > +		} else {
> > +			dev_err(dev, "Unable to add pcie port.\n");
> > +		}
> >  		return ret;
> > +	}
> >
> >  	if (pci_msi_enabled()) {
> >  		u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
>