[PATCH v5 3/4] perf/marvell: cn10k DDR perfmon event overflow handling
Bhaskara Budiredla
bbudiredla at marvell.com
Sun Oct 17 21:37:49 PDT 2021
>Two fixed event counters starts counting from zero on overflow, so overflow
>condition is when new count less than previous count. While eight
>programmable event counters freezes at maximum value. Also individual
>counter cannot be restarted, so need to restart all eight counters.
>
>Signed-off-by: Bharat Bhushan <bbhushan2 at marvell.com>
>---
Reviewed-by: Bhaskara Budiredla <bbudiredla at marvell.com>
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