[PATCH] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary

[Catalin Marinas]

On Wed, Sep 29, 2021 at 12:45:24PM -0700, Peter Collingbourne wrote:
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 2f69ae43941d..85ead6bbb38e 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -269,7 +269,28 @@ alternative_else_nop_endif
>  	.else
>  	add	x21, sp, #PT_REGS_SIZE
>  	get_current_task tsk
> +	ldr	x0, [tsk, THREAD_SCTLR_USER]
>  	.endif /* \el == 0 */
> +
> +	/*
> +	 * Re-enable tag checking (TCO set on exception entry). This is only
> +	 * necessary if MTE is enabled in either the kernel or the userspace
> +	 * task in synchronous mode. With MTE disabled in the kernel and
> +	 * disabled or asynchronous in userspace, tag check faults (including in
> +	 * uaccesses) are not reported, therefore there is no need to re-enable
> +	 * checking. This is beneficial on microarchitectures where re-enabling
> +	 * TCO is expensive.
> +	 */
> +#ifdef CONFIG_ARM64_MTE
> +alternative_cb	kasan_hw_tags_enable
> +	tbz	x0, #SCTLR_EL1_TCF0_SHIFT, 1f
> +alternative_cb_end
> +alternative_if ARM64_MTE
> +	SET_PSTATE_TCO(0)
> +alternative_else_nop_endif
> +1:
> +#endif

I think we can get here from an interrupt as well. Can we guarantee that
the sctlr_user is valid? We are not always in a user process context.

Maybe only do the above checks if \el == 0, otherwise just bracket it
with kasan_hw_tags_enable.

-- 
Catalin