[PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json

[John Garry]

On 04/10/2021 17:00, Andrew Kilroy wrote:
> There are some syntactical mistakes in the json files for the Cortex A76
> N1 (Neoverse N1).  This was obstructing parsing from an external tool.

If the trailing comma is not allowed by standard, then maybe we should 
fix our parsing tool to not allow it also. However maybe there is a good 
reason why we allow it..

Reviewed-by: John Garry <john.garry at huawei.com>

> 
> This patch fixes the erroneous placement of commas causing the problems.
> 
> Signed-off-by: Andrew Kilroy<andrew.kilroy at arm.com>
> ---
>   .../arch/arm64/arm/cortex-a76-n1/branch.json  |  4 +--
>   .../arch/arm64/arm/cortex-a76-n1/bus.json     | 12 +++----
>   .../arch/arm64/arm/cortex-a76-n1/cache.json   | 34 +++++++++----------
>   .../arm64/arm/cortex-a76-n1/exception.json    |  4 +--
>   .../arm64/arm/cortex-a76-n1/instruction.json  | 18 +++++-----
>   .../arch/arm64/arm/cortex-a76-n1/memory.json  |  2 +-
>   .../arch/arm64/arm/cortex-a76-n1/other.json   |  2 +-
>   .../arm64/arm/cortex-a76-n1/pipeline.json     |  4 +--
>   8 files changed, 40 insertions(+), 40 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> index ec0dc92288ab..db68de188390 100644
> --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> @@ -1,10 +1,10 @@
>   [
>       {
>           "PublicDescription": "This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken",
> -        "ArchStdEvent": "BR_MIS_PRED",
> +        "ArchStdEvent": "BR_MIS_PRED"
>       },