[arm:zii 143/161] drivers/net/dsa/qca8k.c:965:47: error: 'port' undeclared
kernel test robot
lkp at intel.com
Wed Nov 24 00:12:17 PST 2021
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git zii
head: 1c86335a03ee0102daaefede1fb25cdbb367b14c
commit: 0d8c1cd8070d6743a8ea65e3b620c454d10a870f [143/161] net: dsa: qca8k: convert to use phylink_pcs
config: i386-randconfig-r024-20211124 (https://download.01.org/0day-ci/archive/20211124/202111241621.Rx9ghHvR-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
git remote add arm git://git.armlinux.org.uk/~rmk/linux-arm.git
git fetch --no-tags arm zii
git checkout 0d8c1cd8070d6743a8ea65e3b620c454d10a870f
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/net/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All errors (new ones prefixed by >>):
In file included from drivers/net/dsa/qca8k.c:22:
drivers/net/dsa/qca8k.c: In function 'qca8k_pcs_get_state':
>> drivers/net/dsa/qca8k.c:965:47: error: 'port' undeclared (first use in this function)
965 | ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®);
| ^~~~
drivers/net/dsa/qca8k.h:70:47: note: in definition of macro 'QCA8K_REG_PORT_STATUS'
70 | #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
| ^~
drivers/net/dsa/qca8k.c:965:47: note: each undeclared identifier is reported only once for each function it appears in
965 | ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®);
| ^~~~
drivers/net/dsa/qca8k.h:70:47: note: in definition of macro 'QCA8K_REG_PORT_STATUS'
70 | #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
| ^~
drivers/net/dsa/qca8k.c: In function 'qca8k_pcs_config':
>> drivers/net/dsa/qca8k.c:1026:22: error: 'ds' undeclared (first use in this function)
1026 | if (dsa_is_cpu_port(ds, port)) {
| ^~
drivers/net/dsa/qca8k.c:1026:26: error: 'port' undeclared (first use in this function)
1026 | if (dsa_is_cpu_port(ds, port)) {
| ^~~~
>> drivers/net/dsa/qca8k.c:1030:13: error: 'state' undeclared (first use in this function); did you mean 'statx'?
1030 | } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
| ^~~~~
| statx
drivers/net/dsa/qca8k.c: In function 'qca8k_phylink_mac_config':
drivers/net/dsa/qca8k.c:1282:6: warning: unused variable 'ret' [-Wunused-variable]
1282 | int ret;
| ^~~
drivers/net/dsa/qca8k.c:1281:11: warning: unused variable 'val' [-Wunused-variable]
1281 | u32 reg, val;
| ^~~
vim +/port +965 drivers/net/dsa/qca8k.c
957
958 static void qca8k_pcs_get_state(struct phylink_pcs *pcs,
959 struct phylink_link_state *state)
960 {
961 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
962 u32 reg;
963 int ret;
964
> 965 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®);
966 if (ret < 0) {
967 state->link = false;
968 return;
969 }
970
971 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
972 state->an_complete = state->link;
973 state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
974 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
975 DUPLEX_HALF;
976
977 switch (reg & QCA8K_PORT_STATUS_SPEED) {
978 case QCA8K_PORT_STATUS_SPEED_10:
979 state->speed = SPEED_10;
980 break;
981 case QCA8K_PORT_STATUS_SPEED_100:
982 state->speed = SPEED_100;
983 break;
984 case QCA8K_PORT_STATUS_SPEED_1000:
985 state->speed = SPEED_1000;
986 break;
987 default:
988 state->speed = SPEED_UNKNOWN;
989 break;
990 }
991
992 state->pause = MLO_PAUSE_NONE;
993 if (reg & QCA8K_PORT_STATUS_RXFLOW)
994 state->pause |= MLO_PAUSE_RX;
995 if (reg & QCA8K_PORT_STATUS_TXFLOW)
996 state->pause |= MLO_PAUSE_TX;
997 }
998
999 static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
1000 phy_interface_t interface,
1001 const unsigned long *advertising,
1002 bool permit_pause_to_mac)
1003 {
1004 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1005 u32 val;
1006 int ret;
1007
1008 /* Enable/disable SerDes auto-negotiation as necessary */
1009 ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1010 if (ret)
1011 return ret;
1012 if (phylink_autoneg_inband(mode))
1013 val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1014 else
1015 val |= QCA8K_PWS_SERDES_AEN_DIS;
1016 qca8k_write(priv, QCA8K_REG_PWS, val);
1017
1018 /* Configure the SGMII parameters */
1019 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1020 if (ret)
1021 return ret;
1022
1023 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1024 QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
1025
> 1026 if (dsa_is_cpu_port(ds, port)) {
1027 /* CPU port, we're talking to the CPU MAC, be a PHY */
1028 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1029 val |= QCA8K_SGMII_MODE_CTRL_PHY;
> 1030 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1031 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1032 val |= QCA8K_SGMII_MODE_CTRL_MAC;
1033 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
1034 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1035 val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1036 }
1037
1038 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1039
1040 return 0;
1041 }
1042
---
0-DAY CI Kernel Test Service, Intel Corporation
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