[PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)

[Ard Biesheuvel]

On Thu, 27 May 2021 at 14:44, Will Deacon <will at kernel.org> wrote:
>
> Back in 97303480753e ("arm64: Increase the max granular size"),
> ARCH_DMA_MINALIGN was effectively increased to 128 bytes thanks to an
> increase in L1_CACHE_BYTES due to an unsubstantiated performance claim
> on the now obsolete ThunderX-1. Although this was reverted in
> d93277b9839b, ARCH_DMA_MINALIGN was kept at 128 bytes by ebc7e21e0fa2
> ("arm64: Increase ARCH_DMA_MINALIGN to 128").
>
> During discussion of the original patch, it was reported that the change
> also prevented a warning during boot on (again, now obsolete) Qualcomm
> server hardware where the cache writeback granule was larger than 64
> bytes. The reason for this warning was because non-coherent DMA could
> lead to data corruption due to unexpected writeback from the CPU where a
> cacheline is shared with other allocations.
>
> Since then, systems have appeared with larger cachelines still, and so
> commit 8f5c9037a55b ("arm64/mm: Correct the cache line size warning with
> non coherent device") reworked the warning so that it only appears on
> systems where non-coherent DMA is actually required and taints the
> kernel with TAINT_CPU_OUT_OF_SPEC. We are not aware of any systems, even
> including the aforementioned obsolete machines, which have a CWG larger
> than 64 bytes and require non-coherent DMA.
>
> More recently, it has been reported that a ARCH_DMA_MINALIGN of 128
> bytes wastes considerable memory (~6% immediately after boot on one
> system).
>
> Reduce ARCH_DMA_MINALIGN to 64 bytes and allow the warning/taint to
> indicate if there are machines that unknowingly rely on this.
>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Cc: Ard Biesheuvel <ardb at kernel.org>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Vincent Whitchurch <vincent.whitchurch at axis.com>
> Link: https://lore.kernel.org/linux-arm-kernel/1442944788-17254-1-git-send-email-rric@kernel.org/
> Link: https://lore.kernel.org/linux-arm-kernel/CAOZdJXUiRMAguDV+HEJqPg57MyBNqEcTyaH+ya=U93NHb-pdJA@mail.gmail.com/
> Link: https://lore.kernel.org/linux-arm-kernel/20190614131141.4428-1-msys.mizuma@gmail.com/
> Link: https://lore.kernel.org/r/20210517074332.28280-1-vincent.whitchurch@axis.com
> Signed-off-by: Will Deacon <will at kernel.org>

Acked-by: Ard Biesheuvel <ardb at kernel.org>

> ---
>  arch/arm64/include/asm/cache.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> index a074459f8f2f..a9c0716e7440 100644
> --- a/arch/arm64/include/asm/cache.h
> +++ b/arch/arm64/include/asm/cache.h
> @@ -47,7 +47,7 @@
>   * cache before the transfer is done, causing old data to be seen by
>   * the CPU.
>   */
> -#define ARCH_DMA_MINALIGN      (128)
> +#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
>
>  #ifdef CONFIG_KASAN_SW_TAGS
>  #define ARCH_SLAB_MINALIGN     (1ULL << KASAN_SHADOW_SCALE_SHIFT)
> --
> 2.31.1.818.g46aad6cb9e-goog
>