[PATCH v2 9/9] arm64: perf: Remove redundant macro and functions in perf_event.c
Qi Liu
liuqi115 at huawei.com
Wed May 19 02:51:59 PDT 2021
Remove ARMV8_EVENT_ATTR and armv8pmu_events_sysfs_show(), as there is
a general function for this.
Cc: Peter Zijlstra <peterz at infradead.org>
Cc: Ingo Molnar <mingo at redhat.com>
Cc: Arnaldo Carvalho de Melo <acme at kernel.org>
Cc: Mark Rutland <mark.rutland at arm.com>
Cc: Alexander Shishkin <alexander.shishkin at linux.intel.com>
Cc: Will Deacon <will at kernel.org>
Signed-off-by: Qi Liu <liuqi115 at huawei.com>
---
arch/arm64/kernel/perf_event.c | 175 +++++++++++++++++++----------------------
1 file changed, 79 insertions(+), 96 deletions(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index f594957..ee9e723 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -153,104 +153,87 @@ static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
};
-static ssize_t
-armv8pmu_events_sysfs_show(struct device *dev,
- struct device_attribute *attr, char *page)
-{
- struct perf_pmu_events_attr *pmu_attr;
-
- pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
-
- return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
-}
-
-#define ARMV8_EVENT_ATTR(name, config) \
- (&((struct perf_pmu_events_attr) { \
- .attr = __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL), \
- .id = config, \
- }).attr.attr)
-
static struct attribute *armv8_pmuv3_event_attrs[] = {
- ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
- ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
- ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
- ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
- ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
- ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
- ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
- ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
- ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
- ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
- ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
- ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
- ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
- ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
- ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
- ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
- ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
- ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
- ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
- ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
- ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
- ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
- ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
- ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
- ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
- ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
- ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
- ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
- ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
- ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
+ PMU_EVENT_ATTR_ID(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
+ PMU_EVENT_ATTR_ID(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
+ PMU_EVENT_ATTR_ID(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
+ PMU_EVENT_ATTR_ID(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
+ PMU_EVENT_ATTR_ID(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
+ PMU_EVENT_ATTR_ID(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
+ PMU_EVENT_ATTR_ID(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
+ PMU_EVENT_ATTR_ID(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
+ PMU_EVENT_ATTR_ID(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
+ PMU_EVENT_ATTR_ID(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
+ PMU_EVENT_ATTR_ID(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
+ PMU_EVENT_ATTR_ID(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
+ PMU_EVENT_ATTR_ID(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
+ PMU_EVENT_ATTR_ID(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
+ PMU_EVENT_ATTR_ID(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
+ PMU_EVENT_ATTR_ID(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
+ PMU_EVENT_ATTR_ID(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
+ PMU_EVENT_ATTR_ID(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
+ PMU_EVENT_ATTR_ID(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
+ PMU_EVENT_ATTR_ID(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
+ PMU_EVENT_ATTR_ID(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
+ PMU_EVENT_ATTR_ID(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
+ PMU_EVENT_ATTR_ID(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
+ PMU_EVENT_ATTR_ID(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
+ PMU_EVENT_ATTR_ID(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
+ PMU_EVENT_ATTR_ID(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
+ PMU_EVENT_ATTR_ID(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
+ PMU_EVENT_ATTR_ID(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
+ PMU_EVENT_ATTR_ID(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
+ PMU_EVENT_ATTR_ID(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
/* Don't expose the chain event in /sys, since it's useless in isolation */
- ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
- ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
- ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
- ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
- ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
- ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
- ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
- ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
- ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
- ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
- ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
- ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
- ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
- ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
- ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
- ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
- ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
- ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
- ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
- ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
- ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
- ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
- ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
- ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
- ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
- ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
- ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
- ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
- ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
- ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
- ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
- ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
- ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
- ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
- ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
- ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
- ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
- ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
- ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
- ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
- ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
- ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
- ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
- ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
- ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
- ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
- ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
- ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
- ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
+ PMU_EVENT_ATTR_ID(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
+ PMU_EVENT_ATTR_ID(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
+ PMU_EVENT_ATTR_ID(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
+ PMU_EVENT_ATTR_ID(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
+ PMU_EVENT_ATTR_ID(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
+ PMU_EVENT_ATTR_ID(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
+ PMU_EVENT_ATTR_ID(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
+ PMU_EVENT_ATTR_ID(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
+ PMU_EVENT_ATTR_ID(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
+ PMU_EVENT_ATTR_ID(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
+ PMU_EVENT_ATTR_ID(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
+ PMU_EVENT_ATTR_ID(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
+ PMU_EVENT_ATTR_ID(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
+ PMU_EVENT_ATTR_ID(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
+ PMU_EVENT_ATTR_ID(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
+ PMU_EVENT_ATTR_ID(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
+ PMU_EVENT_ATTR_ID(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
+ PMU_EVENT_ATTR_ID(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
+ PMU_EVENT_ATTR_ID(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
+ PMU_EVENT_ATTR_ID(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
+ PMU_EVENT_ATTR_ID(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
+ PMU_EVENT_ATTR_ID(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
+ PMU_EVENT_ATTR_ID(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
+ PMU_EVENT_ATTR_ID(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
+ PMU_EVENT_ATTR_ID(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
+ PMU_EVENT_ATTR_ID(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
+ PMU_EVENT_ATTR_ID(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
+ PMU_EVENT_ATTR_ID(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
+ PMU_EVENT_ATTR_ID(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
+ PMU_EVENT_ATTR_ID(stall, ARMV8_PMUV3_PERFCTR_STALL),
+ PMU_EVENT_ATTR_ID(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
+ PMU_EVENT_ATTR_ID(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
+ PMU_EVENT_ATTR_ID(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
+ PMU_EVENT_ATTR_ID(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
+ PMU_EVENT_ATTR_ID(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
+ PMU_EVENT_ATTR_ID(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
+ PMU_EVENT_ATTR_ID(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
+ PMU_EVENT_ATTR_ID(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
+ PMU_EVENT_ATTR_ID(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
+ PMU_EVENT_ATTR_ID(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
+ PMU_EVENT_ATTR_ID(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
+ PMU_EVENT_ATTR_ID(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
+ PMU_EVENT_ATTR_ID(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
+ PMU_EVENT_ATTR_ID(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
+ PMU_EVENT_ATTR_ID(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
+ PMU_EVENT_ATTR_ID(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
+ PMU_EVENT_ATTR_ID(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
+ PMU_EVENT_ATTR_ID(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
+ PMU_EVENT_ATTR_ID(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
NULL,
};
--
2.7.4
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