[PATCH 1/2] arm64: dts: imx8mn: Add spba1 bus

Shawn Guo shawnguo at kernel.org
Mon May 10 19:46:04 PDT 2021


On Mon, Apr 05, 2021 at 08:33:42PM -0500, Adam Ford wrote:
> The i.MX8MN has an SPBA bus which covers much of the audio, but
> there is a second SPBA bus which covers many of the serial interfaces
> like SPI and UARTs currently missing from the device tree. The reference
> manual calls the bus handling the audio peripherals SPBA2, and the bus
> handling the serial peripherals is called SPBA1.
> 
> Rename the existing spba bus to spba2 and add spba1.
> 
> Signed-off-by: Adam Ford <aford173 at gmail.com>
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 4dac4da38f4c..e961acd237a8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -255,7 +255,7 @@ aips1: bus at 30000000 {
>  			#size-cells = <1>;
>  			ranges;
>  
> -			spba: spba-bus at 30000000 {
> +			spba2: spba-bus at 30000000 {
>  				compatible = "fsl,spba-bus", "simple-bus";

Just noticed that "fsl,spba-bus" is undocumented, no?

Also may I ask if you have a real use case for this bus node?

Shawn

>  				#address-cells = <1>;
>  				#size-cells = <1>;
> @@ -681,80 +681,88 @@ aips3: bus at 30800000 {
>  			#size-cells = <1>;
>  			ranges;
>  
> -			ecspi1: spi at 30820000 {
> -				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
> +			spba1: spba-bus at 30800000 {
> +				compatible = "fsl,spba-bus", "simple-bus";
>  				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x30820000 0x10000>;
> -				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
> -					 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
> -				clock-names = "ipg", "per";
> -				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
> -				dma-names = "rx", "tx";
> -				status = "disabled";
> -			};
> +				#size-cells = <1>;
> +				reg = <0x30800000 0x100000>;
> +				ranges;
>  
> -			ecspi2: spi at 30830000 {
> -				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x30830000 0x10000>;
> -				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
> -					 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
> -				clock-names = "ipg", "per";
> -				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
> -				dma-names = "rx", "tx";
> -				status = "disabled";
> -			};
> +				ecspi1: spi at 30820000 {
> +					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x30820000 0x10000>;
> +					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
> +						 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
> +					clock-names = "ipg", "per";
> +					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
> +					dma-names = "rx", "tx";
> +					status = "disabled";
> +				};
>  
> -			ecspi3: spi at 30840000 {
> -				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x30840000 0x10000>;
> -				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
> -					 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
> -				clock-names = "ipg", "per";
> -				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
> -				dma-names = "rx", "tx";
> -				status = "disabled";
> -			};
> +				ecspi2: spi at 30830000 {
> +					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x30830000 0x10000>;
> +					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
> +						 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
> +					clock-names = "ipg", "per";
> +					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
> +					dma-names = "rx", "tx";
> +					status = "disabled";
> +				};
>  
> -			uart1: serial at 30860000 {
> -				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
> -				reg = <0x30860000 0x10000>;
> -				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
> -					 <&clk IMX8MN_CLK_UART1_ROOT>;
> -				clock-names = "ipg", "per";
> -				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
> -				dma-names = "rx", "tx";
> -				status = "disabled";
> -			};
> +				ecspi3: spi at 30840000 {
> +					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x30840000 0x10000>;
> +					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
> +						 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
> +					clock-names = "ipg", "per";
> +					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
> +					dma-names = "rx", "tx";
> +					status = "disabled";
> +				};
>  
> -			uart3: serial at 30880000 {
> -				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
> -				reg = <0x30880000 0x10000>;
> -				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
> -					 <&clk IMX8MN_CLK_UART3_ROOT>;
> -				clock-names = "ipg", "per";
> -				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
> -				dma-names = "rx", "tx";
> -				status = "disabled";
> -			};
> +				uart1: serial at 30860000 {
> +					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
> +					reg = <0x30860000 0x10000>;
> +					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
> +						 <&clk IMX8MN_CLK_UART1_ROOT>;
> +					clock-names = "ipg", "per";
> +					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
> +					dma-names = "rx", "tx";
> +					status = "disabled";
> +				};
>  
> -			uart2: serial at 30890000 {
> -				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
> -				reg = <0x30890000 0x10000>;
> -				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
> -					 <&clk IMX8MN_CLK_UART2_ROOT>;
> -				clock-names = "ipg", "per";
> -				status = "disabled";
> +				uart3: serial at 30880000 {
> +					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
> +					reg = <0x30880000 0x10000>;
> +					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
> +						 <&clk IMX8MN_CLK_UART3_ROOT>;
> +					clock-names = "ipg", "per";
> +					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
> +					dma-names = "rx", "tx";
> +					status = "disabled";
> +				};
> +
> +				uart2: serial at 30890000 {
> +					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
> +					reg = <0x30890000 0x10000>;
> +					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +					clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
> +						 <&clk IMX8MN_CLK_UART2_ROOT>;
> +					clock-names = "ipg", "per";
> +					status = "disabled";
> +				};
>  			};
>  
>  			crypto: crypto at 30900000 {
> -- 
> 2.25.1
> 



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