[PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges

[Lucas Stach]

Am Mittwoch, dem 05.05.2021 um 06:36 -0500 schrieb Adam Ford:
> On Tue, May 4, 2021 at 3:21 AM Lucas Stach <l.stach at pengutronix.de> wrote:
> > 
> > DMA addressing capabilities on i.MX8MM are limited by the interconnect,
> > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
> > the kernel know about this.
> 
> Can you point me to the section of the reference manual where this is
> found?  I'm guessing a similar thing would be applicable to the 8M
> Nano as well, but I want to understand first.

The second patch in this series already fixes up the 8MN DT.

The relevant part of the RM is section 2.1.2 (Cortex-A53 memory map)
where you can see that the DDR above the 4GB mark is only accessible to
the A53 cluster, other DMA masters only have access to the 3GB located
below the 4GB mark.

Regards,
Lucas

> thanks
> 
> adam
> > 
> > Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index 6bf1d15ba16a..5bdc730f6132 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -261,6 +261,7 @@ soc at 0 {
> >                 #address-cells = <1>;
> >                 #size-cells = <1>;
> >                 ranges = <0x0 0x0 0x0 0x3e000000>;
> > +               dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
> >                 nvmem-cells = <&imx8mm_uid>;
> >                 nvmem-cell-names = "soc_unique_id";
> > 
> > --
> > 2.29.2
> > 
> > 
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