[RFC PATCH net-next v3 17/20] net: phy: phylink: permit to pass dev_flags to phylink_connect_phy

[Ansuel Smith]

On Tue, May 04, 2021 at 03:33:36PM -0700, Florian Fainelli wrote:
> On 5/4/21 3:29 PM, Ansuel Smith wrote:
> > Add support for phylink_connect_phy to pass dev_flags to the PHY driver.
> > Change any user of phylink_connect_phy to pass 0 as dev_flags by
> > default.
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth at gmail.com>
> 
> I do not think that this patch and the next one are necessary at all,
> because phylink_of_phy_connect() already supports passing a dev_flags.
> 
> That means that you should be representing the switch's internal MDIO
> bus in the Device Tree and then describe how each port of the switch
> connects to the internal PHY on that same bus. Once you do that the
> logic in net/dsa/slave.c will call phylink_of_phy_connect() and all you
> will have to do is implement dsa_switch_ops::get_phy_flags. Can you try
> that?

I did some testing. Just to make sure I'm correctly implementing this I'm
using the phy-handle binding and the phy-mode set to internal. It does
work with a quick test but I think with this implementation we would be
back to this problem [0].
(I'm declaring the phy_port to the top mdio driver like it was done
before [0])

I was thinking if a good solution would be to register a internal mdio driver
in the qca8k code so that it can use the MASTER reg.
(it's late here so I could be very confused about this)

I think that using this solution we would be able to better describe the phy
by declaring them INSIDE the switch node instead of declaring them
outside in the top mdio node. The internal mdio driver would register
with this new mdio node inside the switch node and use the custom mdio
read/write that use the MASTER reg.

[0] http://patchwork.ozlabs.org/project/netdev/patch/20190319195419.12746-3-chunkeey@gmail.com/

> -- 
> Florian