[PATCH 3/3] ARM: footbridge: restore allocation of CSR I/O resource
Russell King
rmk+kernel at armlinux.org.uk
Fri Mar 26 12:18:18 GMT 2021
Commit 8ef6e6201b2 ("ARM: footbridge: use fixed PCI i/o mapping") made
two changes: it contains what it says in the summary line, but it also
removes the CSR I/O allocation, which effectively means the DC21285
responds to I/O accesses at address 0..0x7f, which overlap Southbridge
ISA resources on the same PCI bus.
This commit fixes it, but depends on the previous two commits removing
the bus level PCI I/O resource:
ARM: footbridge: avoid using separate PCI I/O bus resource
ARM: pci: make bus I/O resources optional
Fixes: 8ef6e6201b2 ("ARM: footbridge: use fixed PCI i/o mapping")
Signed-off-by: Russell King <rmk+kernel at armlinux.org.uk>
---
arch/arm/mach-footbridge/dc21285.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index f9713dc561cf..d900651a9c8f 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -332,6 +332,19 @@ void __init dc21285_preinit(void)
"PCI data parity", NULL);
if (cfn_mode) {
+ static struct resource csrio;
+
+ csrio.flags = IORESOURCE_IO;
+ csrio.name = "Footbridge";
+
+ /*
+ * Put the Footbridge IO space in the top 256 bytes of IO
+ * space, which should otherwise remain unused. This avoids
+ * any conflict with ISA peripherals.
+ */
+ allocate_resource(&ioport_resource, &csrio, 128,
+ 0xff00, 0xffff, 128, NULL, NULL);
+
/*
* Map our SDRAM at a known address in PCI space, just in case
* the firmware had other ideas. Using a nonzero base is
@@ -339,7 +352,7 @@ void __init dc21285_preinit(void)
* in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
*/
*CSR_PCICSRBASE = 0xf4000000;
- *CSR_PCICSRIOBASE = 0;
+ *CSR_PCICSRIOBASE = csrio.start;
*CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
*CSR_PCIROMBASE = 0;
*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
--
2.20.1
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