[PATCH 0/6] PCI: Add legacy interrupt support in Keystone

[Kishon Vijay Abraham I]

Keystone driver is used by K2G and AM65 and the interrupt handling of
both of them is different. Add support to handle legacy interrupt for
both K2G and AM65 here.

Some discussions regarding this was already done here [1] and it was
around having pulse interrupt for legacy interrupt.

The HW interrupt line connected to GIC is a pulse interrupt whereas
the legacy interrupts by definition is level interrupt. In order to
provide level interrupt functionality to edge interrupt line, PCIe
in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.

Patch series also includes converting AM65 binding to YAML and an
errata applicable for i2037.

[1] -> https://lore.kernel.org/linux-arm-kernel/20190221101518.22604-4-kishon@ti.com/

Kishon Vijay Abraham I (6):
  dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's
    AM65 SoC
  dt-bindings: PCI: ti,am65: Add PCIe endpoint mode dt-bindings for TI's
    AM65 SoC
  irqdomain: Export of_phandle_args_to_fwspec()
  PCI: keystone: Convert to using hierarchy domain for legacy interrupts
  PCI: keystone: Add PCI legacy interrupt support for AM654
  PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)

 .../bindings/pci/ti,am65-pci-ep.yaml          |  80 ++++
 .../bindings/pci/ti,am65-pci-host.yaml        | 111 ++++++
 drivers/pci/controller/dwc/pci-keystone.c     | 343 +++++++++++++-----
 include/linux/irqdomain.h                     |   2 +
 kernel/irq/irqdomain.c                        |   6 +-
 5 files changed, 440 insertions(+), 102 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
 create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml

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2.17.1