[PATCH v4 03/19] kvm: arm64: Hide system instruction access to Trace registers

[Suzuki K Poulose]

Will, Catalin,

On 25/02/2021 19:35, Suzuki K Poulose wrote:
> Currently we advertise the ID_AA6DFR0_EL1.TRACEVER for the guest,
> when the trace register accesses are trapped (CPTR_EL2.TTA == 1).
> So, the guest will get an undefined instruction, if trusts the
> ID registers and access one of the trace registers.
> Lets be nice to the guest and hide the feature to avoid
> unexpected behavior.
> 
> Even though this can be done at KVM sysreg emulation layer,
> we do this by removing the TRACEVER from the sanitised feature
> register field. This is fine as long as the ETM drivers
> can handle the individual trace units separately, even
> when there are differences among the CPUs.
> 
> Cc: Marc Zyngier <maz at kernel.org>
> Cc: Will Deacon <will at kernel.org>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>
> ---
> New patch
> ---
>   arch/arm64/kernel/cpufeature.c | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 066030717a4c..a4698f09bf32 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -383,7 +383,6 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
>   	 * of support.
>   	 */
>   	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
> -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
>   	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
>   	ARM64_FTR_END,
>   };
> 

Are you happy to pick this patch for 5.12 as a fix ?

Suzuki