[PATCH 3/4] ARM: dts: imx6ul-14x14-evk: Describe the KSZ8081 reset

Joakim Zhang qiangqing.zhang at nxp.com
Fri Mar 12 02:02:11 GMT 2021


> -----Original Message-----
> From: Andrew Lunn <andrew at lunn.ch>
> Sent: 2021年3月11日 22:18
> To: Joakim Zhang <qiangqing.zhang at nxp.com>
> Cc: Fabio Estevam <festevam at gmail.com>; shawnguo at kernel.org;
> kernel at pengutronix.de; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 3/4] ARM: dts: imx6ul-14x14-evk: Describe the KSZ8081
> reset
> 
> On Thu, Mar 11, 2021 at 11:33:04AM +0000, Joakim Zhang wrote:
> >
> > Hi Fabio, Shawn, Andrew,
> >
> 
> > I found the root cause is the schematic diagram defect, both
> > ENET1_nRST and ENET2_nRST are connect to ENET_nRST, which means PHY0
> > and PHY1 can't be hardware reset independently.
> 
> You can move the reset-gpio up into the MDIO node. It then becomes an MDIO
> bus reset, resetting all PHYs on the bus before they are probed.

Hi Andrew,

I did below change, it can't work. It should be PHY framework have not support multiple reset-gpios for single MDIO bus.
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -203,6 +203,9 @@
        mdio {
                #address-cells = <1>;
                #size-cells = <0>;
+               reset-gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>, <&gpio_spi 2 GPIO_ACTIVE_LOW>;
+               reset-delay-us = <10000>;
+               reset-post-delay-us = <100>;

                ethphy0: ethernet-phy at 2 {
                        compatible = "ethernet-phy-id0022.1560";
@@ -210,9 +213,6 @@
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
                        clock-names = "rmii-ref";
-                       reset-gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
-                       reset-assert-us = <10000>;
-                       reset-deassert-us = <100>;

                };

@@ -222,9 +222,6 @@
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
                        clock-names = "rmii-ref";
-                       reset-gpios = <&gpio_spi 2 GPIO_ACTIVE_LOW>;
-                       reset-assert-us = <10000>;
-                       reset-deassert-us = <100>;
                };
        };
 };

In i.MX6UL 14x14 EVK board, the hareware design is as below:

-----ENET1_nRST---                      -----------IO expander Q1
               |-----------ENET_nRST--------|             
-----ENET2_nRST---                      -----------IO expander Q2 


Best Regards,
Joakim Zhang
>      Andrew


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