[PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0

[Nishanth Menon]

On 19:11-20210311, Pratyush Yadav wrote:
> On 11/03/21 07:22AM, Nishanth Menon wrote:
> > On 21:43-20210305, Vignesh Raghavendra wrote:
> > > 
> > > 
> > > On 3/5/21 9:09 PM, Pratyush Yadav wrote:
> > > > TI J7200 has the Cadence OSPI controller for interfacing with OSPI
> > > > flashes. Add its node to allow using SPI flashes.
> > > > 
> > > > Signed-off-by: Pratyush Yadav <p.yadav at ti.com>
> > > > ---
> > > 
> > > Reviewed-by: Vignesh Raghavendra <vigneshr at ti.com>
> > > 
> > > 
> > > 
> > > > 
> > > > Notes:
> > > >     Changes in v2:
> > > >     - Do not force a pulldown on the DQS line because it already has a
> > > >       pulldown resistor.
> > > > 
> > > >  .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 17 +++++++++
> > > >  arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   | 36 +++++++++++++++++++
> > > >  2 files changed, 53 insertions(+)
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> > > > index 359e3e8a8cd0..5408ec815d58 100644
> > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> > > > @@ -269,6 +269,23 @@ hbmc: hyperbus at 47034000 {
> > > >  			#size-cells = <1>;
> > > >  			mux-controls = <&hbmc_mux 0>;
> > > >  		};
> > > > +
> > > > +		ospi0: spi at 47040000 {
> > > > +			compatible = "ti,am654-ospi";
> > > > +			reg = <0x0 0x47040000 0x0 0x100>,
> > > > +			      <0x5 0x00000000 0x1 0x0000000>;
> > > > +			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> > > > +			cdns,fifo-depth = <256>;
> > > > +			cdns,fifo-width = <4>;
> > > > +			cdns,trigger-address = <0x0>;
> > > > +			clocks = <&k3_clks 103 0>;
> > > > +			assigned-clocks = <&k3_clks 103 0>;
> > > > +			assigned-clock-parents = <&k3_clks 103 2>;
> > > > +			assigned-clock-rates = <166666666>;
> > > > +			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
> > > > +			#address-cells = <1>;
> > > > +			#size-cells = <0>;
> > > > +		};
> > > >  	};
> > > >  
> > > >  	tscadc0: tscadc at 40200000 {
> > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> > > > index a988e2ab2ba1..34724440171a 100644
> > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> > > > @@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
> > > >  			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
> > > >  		>;
> > > >  	};
> > > > +
> > > > +	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
> > > > +		pinctrl-single,pins = <
> > > > +			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
> > > > +			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
> > > > +			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
> > > > +			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
> > > > +			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
> > > > +			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
> > > > +			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
> > > > +			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
> > > > +			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
> > > > +			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
> > > > +			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
> > > > +		>;
> > > > +	};
> > > >  };
> > > >  
> > > >  &main_pmx0 {
> > > > @@ -235,3 +251,23 @@ exp_som: gpio at 21 {
> > > >  				  "GPIO_LIN_EN", "CAN_STB";
> > > >  	};
> > > >  };
> > > > +
> > > > +&ospi0 {
> > > > +	pinctrl-names = "default";
> > > > +	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
> > > > +
> > > > +	flash at 0{
> > > > +		compatible = "jedec,spi-nor";
> > > > +		reg = <0x0>;
> > > > +		spi-tx-bus-width = <8>;
> > > > +		spi-rx-bus-width = <8>;
> > > > +		spi-max-frequency = <25000000>;
> > > > +		cdns,tshsl-ns = <60>;
> > > > +		cdns,tsd2d-ns = <60>;
> > > > +		cdns,tchsh-ns = <60>;
> > > > +		cdns,tslch-ns = <60>;
> > > > +		cdns,read-delay = <4>;
> > > > +		#address-cells = <1>;
> > > > +		#size-cells = <1>;
> > > > +	};
> > I see this:
> > +/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash at 0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+'
> > 
> > 
> > And that is because
> > Documentation/devicetree/bindings/spi/cadence-quadspi.txt is not
> > converted to yaml. Following the new stringent rules, yaml please?
> 
> Ok. I am working on the conversion. Will send it soon.


OK I am keeping to our old rule that as long as binding is pre-existing
and they are in Documentation/devicetree/ we are picking the node up..
new bindings absolutely must be in yaml.

But really, it is high time these txt files get converted to yaml..
Lets use this current collection for 5.13-rc1 cycle as the last window
where we permit this.

* 5.14-rc1 cycle patches, lets make sure: no txt file bindings, yaml at
 least in next
* 5.15-rc1 cycle patches, yaml binding must be in master OR a immutable
  tag from subsystem maintainer.

new bindings already need to be yaml.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D