[PATCH 3/3] clk: socfpga: allow compile testing of Stratix 10 / Agilex clocks

[Arnd Bergmann]

On Tue, Mar 9, 2021 at 10:02 AM Krzysztof Kozlowski
<krzysztof.kozlowski at canonical.com> wrote:

> >
> > Kernel test robot found here wrong configuration - possibility to
> > disable the clocks with compile test. I'll send a v2.
>
> Uh, that's not that easy. Intel created three different arm64 architectures
> for one real arm64 architecture... I guess it was driven by
> the marketing but here we are - the solution would be to have entries like:
>
> bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_AGILEX && !ARCH_N5X && !ARCH_SOCFPGA && !ARCH_STRATIX10
> ...
> bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && !ARCH_AGILEX && !ARCH_N5X && !ARCH_STRATIX10
> ...
> bool "Intel Agilex / N5X clock controller support" if COMPILE_TEST && !ARCH_AGILEX && !ARCH_N5X
> ...
>
> I think it looks wrong. The stratix/agilex/n5x are basically flavors of
> socfpga from Linux point of view. This is the same architecture for Linux
> kernel, from high level point of view. Instead of going with unified ARCH_SOCFPGA
> (like all other platforms, e.g. Renesas, NXP), the Intel create three
> different kernel-wide arm64 ARCH_xxx symbols.
>
> It's too much. How about converting all these arm64 Intel platforms to ARCH_SOCFPGA?

Agreed, that seems best here.  There is no need at all to have multiple
top-level Kconfig symbols when these are all part of one SoC family.

       Arnd