[PATCH v5 09/18] arm64: dts: imx8: switch to two cell scu clock binding
Dong Aisheng
aisheng.dong at nxp.com
Fri Mar 5 13:17:39 GMT 2021
switch to two cell scu clock binding
Signed-off-by: Dong Aisheng <aisheng.dong at nxp.com>
---
ChangeLog:
v2->v5:
* no changes except rebase
v1->v2:
* split from lpcg binding changes
---
.../boot/dts/freescale/imx8-ss-adma.dtsi | 24 +++----
.../boot/dts/freescale/imx8-ss-conn.dtsi | 14 ++--
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 64 ++++++++++++-------
.../boot/dts/freescale/imx8qxp-ai_ml.dts | 4 +-
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 10 +--
6 files changed, 68 insertions(+), 52 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 9301166ea629..30f2089cfdc4 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -113,7 +113,7 @@ adma_lpuart3: serial at 5a090000 {
uart0_lpcg: clock-controller at 5a460000 {
reg = <0x5a460000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART0_CLK>,
+ clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart0_lpcg_baud_clk",
@@ -124,7 +124,7 @@ uart0_lpcg: clock-controller at 5a460000 {
uart1_lpcg: clock-controller at 5a470000 {
reg = <0x5a470000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART1_CLK>,
+ clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart1_lpcg_baud_clk",
@@ -135,7 +135,7 @@ uart1_lpcg: clock-controller at 5a470000 {
uart2_lpcg: clock-controller at 5a480000 {
reg = <0x5a480000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART2_CLK>,
+ clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart2_lpcg_baud_clk",
@@ -146,7 +146,7 @@ uart2_lpcg: clock-controller at 5a480000 {
uart3_lpcg: clock-controller at 5a490000 {
reg = <0x5a490000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART3_CLK>,
+ clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart3_lpcg_baud_clk",
@@ -159,7 +159,7 @@ adma_i2c0: i2c at 5a800000 {
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_0>;
status = "disabled";
@@ -170,7 +170,7 @@ adma_i2c1: i2c at 5a810000 {
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_1>;
status = "disabled";
@@ -181,7 +181,7 @@ adma_i2c2: i2c at 5a820000 {
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_2>;
status = "disabled";
@@ -192,7 +192,7 @@ adma_i2c3: i2c at 5a830000 {
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
@@ -201,7 +201,7 @@ adma_i2c3: i2c at 5a830000 {
i2c0_lpcg: clock-controller at 5ac00000 {
reg = <0x5ac00000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C0_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c0_lpcg_clk",
@@ -212,7 +212,7 @@ i2c0_lpcg: clock-controller at 5ac00000 {
i2c1_lpcg: clock-controller at 5ac10000 {
reg = <0x5ac10000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C1_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c1_lpcg_clk",
@@ -223,7 +223,7 @@ i2c1_lpcg: clock-controller at 5ac10000 {
i2c2_lpcg: clock-controller at 5ac20000 {
reg = <0x5ac20000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C2_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c2_lpcg_clk",
@@ -234,7 +234,7 @@ i2c2_lpcg: clock-controller at 5ac20000 {
i2c3_lpcg: clock-controller at 5ac30000 {
reg = <0x5ac30000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C3_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c3_lpcg_clk",
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 4220a5cdc249..83945cc720e1 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -112,7 +112,7 @@ conn_lpcg: clock-controller-legacy at 5b200000 {
sdhc0_lpcg: clock-controller at 5b200000 {
reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_SDHC0_CLK>,
+ clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
@@ -125,7 +125,7 @@ sdhc0_lpcg: clock-controller at 5b200000 {
sdhc1_lpcg: clock-controller at 5b210000 {
reg = <0x5b210000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_SDHC1_CLK>,
+ clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
@@ -138,7 +138,7 @@ sdhc1_lpcg: clock-controller at 5b210000 {
sdhc2_lpcg: clock-controller at 5b220000 {
reg = <0x5b220000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_SDHC2_CLK>,
+ clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
@@ -151,8 +151,8 @@ sdhc2_lpcg: clock-controller at 5b220000 {
enet0_lpcg: clock-controller at 5b230000 {
reg = <0x5b230000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
- <&clk IMX_CONN_ENET0_ROOT_CLK>,
+ clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
@@ -168,8 +168,8 @@ enet0_lpcg: clock-controller at 5b230000 {
enet1_lpcg: clock-controller at 5b240000 {
reg = <0x5b240000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
- <&clk IMX_CONN_ENET1_ROOT_CLK>,
+ clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index babe6c3e2c76..813dbac71d10 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -157,9 +157,11 @@ lsio_lpcg: clock-controller-legacy at 5d400000 {
pwm0_lpcg: clock-controller at 5d400000 {
reg = <0x5d400000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM0_CLK>, <&clk IMX_LSIO_PWM0_CLK>,
- <&clk IMX_LSIO_PWM0_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM0_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -174,9 +176,11 @@ pwm0_lpcg: clock-controller at 5d400000 {
pwm1_lpcg: clock-controller at 5d410000 {
reg = <0x5d410000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM1_CLK>, <&clk IMX_LSIO_PWM1_CLK>,
- <&clk IMX_LSIO_PWM1_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM1_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -191,9 +195,11 @@ pwm1_lpcg: clock-controller at 5d410000 {
pwm2_lpcg: clock-controller at 5d420000 {
reg = <0x5d420000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM2_CLK>, <&clk IMX_LSIO_PWM2_CLK>,
- <&clk IMX_LSIO_PWM2_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM2_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -208,9 +214,11 @@ pwm2_lpcg: clock-controller at 5d420000 {
pwm3_lpcg: clock-controller at 5d430000 {
reg = <0x5d430000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM3_CLK>, <&clk IMX_LSIO_PWM3_CLK>,
- <&clk IMX_LSIO_PWM3_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM3_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -225,9 +233,11 @@ pwm3_lpcg: clock-controller at 5d430000 {
pwm4_lpcg: clock-controller at 5d440000 {
reg = <0x5d440000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM4_CLK>, <&clk IMX_LSIO_PWM4_CLK>,
- <&clk IMX_LSIO_PWM4_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM4_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -242,9 +252,11 @@ pwm4_lpcg: clock-controller at 5d440000 {
pwm5_lpcg: clock-controller at 5d450000 {
reg = <0x5d450000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM5_CLK>, <&clk IMX_LSIO_PWM5_CLK>,
- <&clk IMX_LSIO_PWM5_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM5_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -259,9 +271,11 @@ pwm5_lpcg: clock-controller at 5d450000 {
pwm6_lpcg: clock-controller at 5d460000 {
reg = <0x5d460000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM6_CLK>, <&clk IMX_LSIO_PWM6_CLK>,
- <&clk IMX_LSIO_PWM6_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM6_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -276,9 +290,11 @@ pwm6_lpcg: clock-controller at 5d460000 {
pwm7_lpcg: clock-controller at 5d470000 {
reg = <0x5d470000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM7_CLK>, <&clk IMX_LSIO_PWM7_CLK>,
- <&clk IMX_LSIO_PWM7_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM7_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
index a3f8cf195974..b5352706e3f0 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
@@ -133,7 +133,7 @@ ethphy0: ethernet-phy at 0 {
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
- assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -151,7 +151,7 @@ brcmf: wifi at 1 {
/* SD */
&usdhc2 {
- assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 46437d3c7a04..c40bbb313b78 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -173,7 +173,7 @@ map0 {
};
&usdhc1 {
- assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -185,7 +185,7 @@ &usdhc1 {
};
&usdhc2 {
- assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index cd7a482dc3ff..095d3f69a9b7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -58,7 +58,7 @@ A35_0: cpu at 0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -69,7 +69,7 @@ A35_1: cpu at 1 {
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -80,7 +80,7 @@ A35_2: cpu at 2 {
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -91,7 +91,7 @@ A35_3: cpu at 3 {
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -165,7 +165,7 @@ pd: imx8qx-pd {
clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
- #clock-cells = <1>;
+ #clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
--
2.25.1
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