[PATCH net 1/1] net: stmmac: fix incorrect DMA channel intr enable setting of EQoS v4.10

[Joakim Zhang]

> -----Original Message-----
> From: ramesh.babu.b at intel.com <ramesh.babu.b at intel.com>
> Sent: 2021年3月3日 23:09
> To: Giuseppe Cavallaro <peppe.cavallaro at st.com>; Alexandre Torgue
> <alexandre.torgue at st.com>; Jose Abreu <joabreu at synopsys.com>; David S .
> Miller <davem at davemloft.net>; Jakub Kicinski <kuba at kernel.org>; Maxime
> Coquelin <mcoquelin.stm32 at gmail.com>
> Cc: netdev at vger.kernel.org; linux-stm32 at st-md-mailman.stormreply.com;
> linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org; Ong Boon
> Leong <boon.leong.ong at intel.com>; Voon Wei Feng
> <weifeng.voon at intel.com>; Wong Vee Khee <vee.khee.wong at intel.com>;
> Ramesh Babu B <ramesh.babu.b at intel.com>
> Subject: [PATCH net 1/1] net: stmmac: fix incorrect DMA channel intr enable
> setting of EQoS v4.10
> 
> From: Ong Boon Leong <boon.leong.ong at intel.com>
> 
> We introduce dwmac410_dma_init_channel() here for both EQoS v4.10 and
> above which use different DMA_CH(n)_Interrupt_Enable bit definitions for NIE
> and AIE.
> 
> Fixes: 48863ce5940f ("stmmac: add DMA support for GMAC 4.xx")
> Signed-off-by: Ong Boon Leong <boon.leong.ong at intel.com>
> Signed-off-by: Ramesh Babu B <ramesh.babu.b at intel.com>

Reviewed-by: Joakim Zhang <qiangqing.zhang at nxp.com>

Best Regards,
Joakim Zhang
> ---
>  .../net/ethernet/stmicro/stmmac/dwmac4_dma.c  | 19
> ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
> b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
> index bb29bfcd62c3..62aa0e95beb7 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
> @@ -124,6 +124,23 @@ static void dwmac4_dma_init_channel(void __iomem
> *ioaddr,
>  	       ioaddr + DMA_CHAN_INTR_ENA(chan));  }
> 
> +static void dwmac410_dma_init_channel(void __iomem *ioaddr,
> +				      struct stmmac_dma_cfg *dma_cfg, u32 chan) {
> +	u32 value;
> +
> +	/* common channel control register config */
> +	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
> +	if (dma_cfg->pblx8)
> +		value = value | DMA_BUS_MODE_PBL;
> +
> +	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
> +
> +	/* Mask interrupts by writing to CSR7 */
> +	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
> +	       ioaddr + DMA_CHAN_INTR_ENA(chan)); }
> +
>  static void dwmac4_dma_init(void __iomem *ioaddr,
>  			    struct stmmac_dma_cfg *dma_cfg, int atds)  { @@
> -523,7 +540,7 @@ const struct stmmac_dma_ops dwmac4_dma_ops =
> {  const struct stmmac_dma_ops dwmac410_dma_ops = {
>  	.reset = dwmac4_dma_reset,
>  	.init = dwmac4_dma_init,
> -	.init_chan = dwmac4_dma_init_channel,
> +	.init_chan = dwmac410_dma_init_channel,
>  	.init_rx_chan = dwmac4_dma_init_rx_chan,
>  	.init_tx_chan = dwmac4_dma_init_tx_chan,
>  	.axi = dwmac4_dma_axi,
> --
> 2.17.1