[PATCH 2/2] soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain

[Peng Fan (OSS)]

> Subject: [PATCH 2/2] soc: imx: gpcv2: Set both
> GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain
> 
> To bring up the MX8MM GPU domain, it is necessary to configure both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without
> this configuration, the system might hang on boot when bringing up the GPU
> power domain. This is sporadically observed on multiple disparate systems.
> 
> Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both
> GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are
> configured when bringing up the GPU domain. This fixes the sporadic hang.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Frieder Schrempf <frieder.schrempf at kontron.de>
> Cc: Lucas Stach <l.stach at pengutronix.de>
> Cc: NXP Linux Team <linux-imx at nxp.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Shawn Guo <shawnguo at kernel.org>
> ---
>  drivers/soc/imx/gpcv2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 1cf23144d5378..fd1d15c6cf561 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -698,7 +698,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
>  			.hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
>  			.hskack = IMX8MM_GPU_HSK_PWRDNACKN,
>  		},
> -		.pgc   = BIT(IMX8MM_PGC_GPU2D),
> +		.pgc   = BIT(IMX8MM_PGC_GPU2D) |
> BIT(IMX8MM_PGC_GPU3D),

This is indeed needed. GPU2D,3D for 8MM should be power up/off together.

Reviewed-by: Peng Fan <peng.fan at nxp.com>

>  		/* Assert reset, power up domain, deassert reset */
>  		.reset_assert_early = true,
>  		.reset_deassert_early = false,
> --
> 2.30.2