[PATCH v4 6/7] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data

[Stephen Boyd]

Quoting Alain Volmat (2021-03-31 13:16:31)
> In order to avoid relying on the old style description via the DT
> clock-output-names, add compatible data describing the flexgen
> outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
> 
> In order to ease transition between the two methods, this commit
> introduce the new compatible without removing the old method.
> Once DTs will be fixed, the method relying on DT clock-output-names
> will be removed from this driver as well as old compatibles.
> 
> Signed-off-by: Alain Volmat <avolmat at me.com>
> Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>
> ---

Applied to clk-next