[PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's

[Geert Uytterhoeven]

Hi Biju,

On Fri, Jun 4, 2021 at 3:55 PM Biju Das <biju.das.jz at bp.renesas.com> wrote:
> > Subject: [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for
> > RZ/G2{L,LC} SoC's
> >
> > Add initial DTSI for RZ/G2{L,LC} SoC's.
> >
> > File structure:
> > r9a07g044.dtsi  => RZ/G2L family SoC common parts r9a07g044l1.dtsi =>
> > Specific to RZ/G2L (R9A07G044L single cortex A55) SoC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > Signed-off-by: Biju Das <biju.das.jz at bp.renesas.com>

> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi

> > +             cpg: clock-controller at 11010000 {
> > +                     compatible = "renesas,r9a07g044-cpg";
> > +                     reg = <0 0x11010000 0 0x10000>;
>
> What about WDTOVF_RST(0xB10) and WDTRST_SEL(0xB14) registers, this registers to be handled by WDT driver.
> Unfortunately it is in CPG block.
>
> So do we need to map the entire CPG registers or up to 0xB00?
>
> Geert, Prabhakar: Any thoughts?

As the registers are part of the CPG block, I think they should be
covered by the CPG node.  You can handle them in the CPG driver, through
functions called from the WDT driver (cfr. rcar_rst_read_mode_pins()).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

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