[PATCH] ARM: dts: ixp4xx: Add devicetree for Linksys WRV54G
Andrew Lunn
andrew at lunn.ch
Thu Jul 29 08:33:26 PDT 2021
> + /* This set-up comes from an OpenWrt patch */
> + spi {
> + compatible = "spi-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
> + miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
> + mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
> + num-chipselects = <1>;
> +
> + switch at 0 {
> + compatible = "micrel,ks8995";
Hi Linus
This does not exist in mainline. And when it does, i guess it will be
called microchip,ksz8995. See microchip,ksz.yaml. It is also missing
all the ethernet-ports nodes. Maybe leave this out until the driver
gets ported?
> + /*
> + * EthB - connected to the KS8995 switch ports 1-4
> + * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
> + * all four switch ports, also using an out of tree multiphy patch.
> + * Do we need a new binding and property for this?
> + */
This sounds like an issue with the KS8995 driver in OpenWRT.
> + ethernet at c8009000 {
> + status = "ok";
> + queue-rx = <&qmgr 3>;
> + queue-txready = <&qmgr 20>;
> + phy-mode = "rgmii";
> + phy-handle = <&phy4>;
It looks like phy4 is a switch PHY. It is not actually connected to
this MAC? So this is wrong for mainline.
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* Should be ports 1-4 on the KS8995 switch */
> + phy4: ethernet-phy at 4 {
> + reg = <4>;
> + };
> +
> + /* Should be port 5 on the KS8995 switch */
> + phy5: ethernet-phy at 5 {
> + reg = <5>;
> + };
> + };
> + };
> +
> + /* EthC - connected to KS8995 switch port 5 */
> + ethernet at c800a000 {
> + status = "ok";
> + queue-rx = <&qmgr 4>;
> + queue-txready = <&qmgr 21>;
> + phy-mode = "rgmii";
> + phy-handle = <&phy5>;
And i doubt this is correct. Unless there are back to back PHYs?
I would suggest you leave out all the switch related properties until
the switch driver is available.
Andrew
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