[PATCH v5] arm64: avoid double ISB on kernel entry

[Catalin Marinas]

On Tue, 27 Jul 2021 13:54:39 -0700, Peter Collingbourne wrote:
> Although an ISB is required in order to make the MTE-related system
> register update to GCR_EL1 effective, and the same is true for
> PAC-related updates to SCTLR_EL1 or APIAKey{Hi,Lo}_EL1, we issue two
> ISBs on machines that support both features while we only need to
> issue one. To avoid the unnecessary additional ISB, remove the ISBs
> from the PAC and MTE-specific alternative blocks and add a couple
> of additional blocks that cause us to only execute one ISB if both
> features are supported.

Applied to arm64 (for-next/mte). It still conflicted, so please check
that the result is fine. Thanks!

[1/1] arm64: avoid double ISB on kernel entry
      https://git.kernel.org/arm64/c/d914b80a8f56

-- 
Catalin