[PATCH v4] arm64: mte: optimize GCR_EL1 modification on kernel entry/exit

[Catalin Marinas]

On Wed, Jul 14, 2021 at 03:04:42PM +0100, Mark Rutland wrote:
> On Tue, Jul 13, 2021 at 06:36:38PM -0700, Peter Collingbourne wrote:
> > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> > index ce59280355c5..2d6dc62d929a 100644
> > --- a/arch/arm64/kernel/entry.S
> > +++ b/arch/arm64/kernel/entry.S
> > @@ -175,15 +175,11 @@ alternative_else_nop_endif
> >  #endif
> >  	.endm
> >  
> > -	.macro mte_set_gcr, tmp, tmp2
> > +	.macro mte_set_gcr, mte_ctrl, tmp
> >  #ifdef CONFIG_ARM64_MTE
> > -	/*
> > -	 * Calculate and set the exclude mask preserving
> > -	 * the RRND (bit[16]) setting.
> > -	 */
> > -	mrs_s	\tmp2, SYS_GCR_EL1
> > -	bfxil	\tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
> > -	msr_s	SYS_GCR_EL1, \tmp2
> > +	ubfx	\tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
> > +	orr	\tmp, \tmp, #SYS_GCR_EL1_RRND
> > +	msr_s	SYS_GCR_EL1, \tmp
> >  #endif
> >  	.endm
> 
> Since the mte_ctrl value only has the Exclude bits set, we can make this
> even simpler:
> 
> 	orr	\tmp, \mte_ctrl, #SYS_GCR_EL1_RRND
> 	msr_s   SYS_GCR_EL1, \tmp

I don't think we can guarantee it following this patch (some other bits
added to mte_ctrl):

https://lore.kernel.org/r/20210727205300.2554659-3-pcc@google.com

-- 
Catalin