[PATCH 1/2] ARM: dts: ixp4xx: Add Intel IXDP425 etc reference designs
Linus Walleij
linus.walleij at linaro.org
Tue Jul 27 16:16:48 PDT 2021
The IXDP425, IXCDP1100, KIXRP435 and IXDP465 are similar Intel reference
designs for IXP42x, IXP43x and IXP4[56]x.
This adds device trees for these so the board files can be migrated.
Cc: Deepak Saxena <dsaxena at plexity.net>
Cc: Vladimir Barinov <vladimir.barinov at cogentembedded.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Vladimir: I only have a stub for the NAND, I don't find any
references to this NAND chip in the Intel user guides, so if you
want me to fix this up better I need more information on this.
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/intel-ixp42x-ixdp425.dts | 72 ++++++++++
arch/arm/boot/dts/intel-ixp43x-kixrp435.dts | 68 +++++++++
arch/arm/boot/dts/intel-ixp46x-ixdp465.dts | 38 +++++
.../dts/intel-ixp4xx-reference-design.dtsi | 132 ++++++++++++++++++
5 files changed, 313 insertions(+)
create mode 100644 arch/arm/boot/dts/intel-ixp42x-ixdp425.dts
create mode 100644 arch/arm/boot/dts/intel-ixp43x-kixrp435.dts
create mode 100644 arch/arm/boot/dts/intel-ixp46x-ixdp465.dts
create mode 100644 arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b07ebae2f56e..68308d199cf4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -242,6 +242,9 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp42x-linksys-nslu2.dtb \
intel-ixp42x-welltech-epbx100.dtb \
+ intel-ixp42x-ixdp425.dtb \
+ intel-ixp43x-kixrp435.dtb \
+ intel-ixp46x-ixdp465.dtb \
intel-ixp42x-iomega-nas100d.dtb \
intel-ixp42x-dlink-dsm-g600.dtb \
intel-ixp42x-gateworks-gw2348.dtb \
diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts
new file mode 100644
index 000000000000..beaadda4685f
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
+ * processor reference design.
+ *
+ * This platform has the codename "Richfield".
+ *
+ * This machine is based on a 533 MHz IXP425.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+#include "intel-ixp4xx-reference-design.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Intel IXDP425/IXCDP1100 Richfield Reference Design";
+ compatible = "intel,ixdp425", "intel,ixp42x";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc {
+ bus at c4000000 {
+ flash at 0,0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /* Enable writes on the expansion bus */
+ intel,ixp4xx-eb-write-enable = <1>;
+ /* 16 MB of Flash mapped in at CS0 */
+ reg = <0 0x00000000 0x1000000>;
+
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x0fe0000 */
+ fis-index-block = <0x7f>;
+ };
+ };
+ };
+
+ /* EthB */
+ ethernet at c8009000 {
+ status = "ok";
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ /* EthC */
+ ethernet at c800a000 {
+ status = "ok";
+ queue-rx = <&qmgr 4>;
+ queue-txready = <&qmgr 21>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts b/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts
new file mode 100644
index 000000000000..3d7cfa1a5ed4
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Intel KIXRP435 Control Plane
+ * processor reference design.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp43x.dtsi"
+#include "intel-ixp4xx-reference-design.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Intel KIXRP435 Reference Design";
+ compatible = "intel,kixrp435", "intel,ixp43x";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc {
+ bus at c4000000 {
+ flash at 0,0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /* Enable writes on the expansion bus */
+ intel,ixp4xx-eb-write-enable = <1>;
+ /* 16 MB of Flash mapped in at CS0 */
+ reg = <0 0x00000000 0x1000000>;
+
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x0fe0000 */
+ fis-index-block = <0x7f>;
+ };
+ };
+ };
+
+ /* CHECKME: ethernet set-up taken from Gateworks Cambria */
+ ethernet at c800a000 {
+ status = "ok";
+ queue-rx = <&qmgr 4>;
+ queue-txready = <&qmgr 21>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy at 2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ ethernet at c800c000 {
+ status = "ok";
+ queue-rx = <&qmgr 2>;
+ queue-txready = <&qmgr 19>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy2>;
+ intel,npe-handle = <&npe 0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts b/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts
new file mode 100644
index 000000000000..a062cd1a6588
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Intel IXDP465 Control Plane processor reference
+ * design, codename "BMP".
+ */
+
+/dts-v1/;
+
+#include "intel-ixp45x-ixp46x.dtsi"
+#include "intel-ixp4xx-reference-design.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Intel IXDP465 BMP Reference Design";
+ compatible = "intel,ixdp465", "intel,ixp46x";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc {
+ bus at c4000000 {
+ flash at 0,0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /* Enable writes on the expansion bus */
+ intel,ixp4xx-eb-write-enable = <1>;
+ /* 32 MB of Flash mapped in at CS0 and CS1 */
+ reg = <0 0x00000000 0x2000000>;
+
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x1fe0000 */
+ fis-index-block = <0xff>;
+ };
+ };
+ };
+ /* TODO: configure ethernet etc */
+ };
+};
diff --git a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
new file mode 100644
index 000000000000..f72e1362717d
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree include file for Intel reference designs for the
+ * XScale Network Processors in the IXP 4xx series. Common device
+ * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
+ */
+
+/ {
+ memory at 0 {
+ /*
+ * The board supports up to 256 MB of memory. Here we put in
+ * 64 MB and this may be modified by the boot loader.
+ */
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = "uart0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ i2c {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom at 50 {
+ /*
+ * Philips PCF8582C-2T/03 512byte I2C EEPROM
+ * should behave like an Atmel 24c04.
+ */
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ size = <512>;
+ read-only;
+ };
+ };
+
+ soc {
+ bus at c4000000 {
+ /* Flash memory defined per-variant */
+ nand-controller at 3,0 {
+ /* Some designs have a NAND on CS3 enable it here if present */
+ status = "disabled";
+
+ /*
+ * gen_nand needs to be extended and documented to get
+ * command byte = 1 and address byte = 2 from the device
+ * tree.
+ */
+ compatible = "gen_nand";
+
+ /* Expansion bus set-up */
+ intel,ixp4xx-eb-t1 = <0>;
+ intel,ixp4xx-eb-t2 = <0>;
+ intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
+ intel,ixp4xx-eb-t4 = <0>;
+ intel,ixp4xx-eb-t5 = <0>;
+ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
+ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
+ intel,ixp4xx-eb-mux-address-and-data = <0>;
+ intel,ixp4xx-eb-ahb-split-transfers = <0>;
+ intel,ixp4xx-eb-write-enable = <1>;
+ intel,ixp4xx-eb-byte-access = <1>;
+
+ /* 512 bytes memory window */
+ reg = <3 0x00000000 0x200>;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "soft_bch";
+ nand-ecc-step-size = <512>;
+ nand-ecc-strength = <4>;
+ nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */
+
+ label = "ixp400 NAND";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fs at 0 {
+ label = "ixp400 NAND FS 0";
+ reg = <0x0 0x800000>;
+ };
+ fs at 800000 {
+ label = "ixp400 NAND FS 1";
+ reg = <0x800000 0x0>;
+ };
+ };
+ };
+ };
+
+ pci at c0000000 {
+ status = "ok";
+
+ /*
+ * Taken from IXDP425 PCI boardfile.
+ * PCI slots on the BIXMB425BD base card.
+ * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
+ */
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+ /* IDSEL 2 */
+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
+ <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
+ <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
+ /* IDSEL 3 */
+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
+ <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
+ <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
+ <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
+ /* IDSEL 4 */
+ <0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 4 is irq 8 */
+ <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 4 is irq 11 */
+ <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 4 is irq 10 */
+ <0x2000 0 0 4 &gpio0 9 3>; /* INT D on slot 4 is irq 9 */
+ };
+ };
+};
--
2.31.1
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