[PATCH 1/2 v3] bus: ixp4xx: Add DT bindings for the IXP4xx expansion bus

[Rob Herring]

On Tue, Jul 27, 2021 at 2:09 AM Linus Walleij <linus.walleij at linaro.org> wrote:
>
> This adds device tree bindings for the IXP4xx expansion bus controller.
>
> Cc: Marc Zyngier <maz at kernel.org>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> ChangeLog v2->v3:
> - Add syscon as second compatible. The device contains a set
>   of misc registers apart from the chip select control.
> - Add required "native-endianness" flag on the node and describe
>   why.
> - Change bool flags into enum [0, 1]. The reason is that we
>   need to be able to indicate clearly that we want an option to
>   be zeroed as the OS will read/modify/write the config from the
>   bootloader/power-on-defaults which sometimes means disabling
>   things that would only be possibel to turn on with flags.
> ChangeLog v1->v2:
> - Drop unevaluatedProperties: false from the node match.
>   additionalProperties: true will be the default.
> ---
>  ...intel,ixp4xx-expansion-bus-controller.yaml | 168 ++++++++++++++++++
>  1 file changed, 168 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
>
> diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
> new file mode 100644
> index 000000000000..bd569670bca9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
> @@ -0,0 +1,168 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel IXP4xx Expansion Bus Controller
> +
> +description: |
> +  The IXP4xx expansion bus controller handles access to devices on the
> +  memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
> +  including IXP42x, IXP43x, IXP45x and IXP46x.
> +
> +maintainers:
> +  - Linus Walleij <linus.walleij at linaro.org>
> +
> +properties:
> +  $nodename:
> +    pattern: '^bus@[0-9a-f]+$'
> +
> +  compatible:
> +    items:
> +      - enum:
> +          - intel,ixp42x-expansion-bus-controller
> +          - intel,ixp43x-expansion-bus-controller
> +          - intel,ixp45x-expansion-bus-controller
> +          - intel,ixp46x-expansion-bus-controller
> +      - const: syscon
> +
> +  reg:
> +    description: Control registers for the expansion bus, these are not
> +      inside the memory range handled by the expansion bus.
> +    maxItems: 1
> +
> +  native-endian:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: The IXP4xx has a peculiar MMIO access scheme, as it changes
> +      the access pattern for words (swizzling) on the bus depending on whether
> +      the SoC is running in big-endian or little-endian mode. Thus the
> +      registers must always be accessed using native endianness.
> +
> +  "#address-cells":
> +    description: |
> +      The first cell is the chip select numer.

typo

Otherwise,

Reviewed-by: Rob Herring <robh at kernel.org>