[PATCH] ARM: dts: ixp4xx: Add devicetree for Netgear WG302v2

[Linus Walleij]

This adds a devicetree for the Netgear WG302v2 router.

The DTS is mostly based on the upstream boardfile but I also
added in the ethernet from OpenWrt to get a more complete
system.

Cc: Imre Kaloz <kaloz at openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/Makefile                    |  3 +-
 .../boot/dts/intel-ixp42x-netgear-wg302v2.dts | 95 +++++++++++++++++++
 2 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1de207f19821..5500eac49eae 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
 	intel-ixp43x-gateworks-gw2358.dtb \
 	intel-ixp42x-omicron-devixp.dtb \
 	intel-ixp42x-omicron-miccpt.dtb \
-	intel-ixp42x-omicron-mic256.dtb
+	intel-ixp42x-omicron-mic256.dtb \
+	intel-ixp42x-netgear-wg302v2.dtb
 dtb-$(CONFIG_ARCH_KEYSTONE) += \
 	keystone-k2hk-evm.dtb \
 	keystone-k2l-evm.dtb \
diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
new file mode 100644
index 000000000000..6c1f3c6a0e84
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Netgear WG302v2 based on IXP422BB
+ * Derived from boardfiles written by Imre Kaloz
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Netgear WG302 v2";
+	compatible = "netgear,wg302v2", "intel,ixp42x";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory at 0 {
+		/* 16 MB SDRAM according to OpenWrt database */
+		device_type = "memory";
+		reg = <0x00000000 0x01000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+		stdout-path = "uart1:115200n8";
+	};
+
+	aliases {
+		/* These are switched around */
+		serial0 = &uart1;
+		serial1 = &uart0;
+	};
+
+	soc {
+		bus at c4000000 {
+			flash at 0,0 {
+				compatible = "intel,ixp4xx-flash", "cfi-flash";
+				bank-width = <2>;
+				/*
+				 * 32 MB of Flash in 128 0x20000 sized blocks
+				 * mapped in at CS0 and CS1
+				 */
+				reg = <0 0x00000000 0x2000000>;
+
+				/* Configure expansion bus to allow writes */
+				intel,ixp4xx-eb-write-enable;
+
+				partitions {
+					compatible = "redboot-fis";
+					/* CHECKME: guess this is Redboot FIS */
+					fis-index-block = <0xff>;
+				};
+			};
+		};
+
+		pci at c0000000 {
+			status = "ok";
+
+			/*
+			 * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c)
+			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
+			 * each handling all IRQs.
+			 */
+			interrupt-map =
+			/* IDSEL 1 */
+			<0x0800 0 0 1 &gpio0 8 3>, /* INT A on slot 1 is irq 8 */
+			<0x0800 0 0 2 &gpio0 8 3>, /* INT B on slot 1 is irq 8 */
+			<0x0800 0 0 3 &gpio0 8 3>, /* INT C on slot 1 is irq 8 */
+			<0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+			/* IDSEL 2 */
+			<0x1000 0 0 1 &gpio0 9 3>, /* INT A on slot 2 is irq 9 */
+			<0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
+			<0x1000 0 0 3 &gpio0 9 3>, /* INT C on slot 2 is irq 9 */
+			<0x1000 0 0 4 &gpio0 9 3>; /* INT D on slot 2 is irq 9 */
+		};
+
+		ethernet at c8009000 {
+			status = "ok";
+			queue-rx = <&qmgr 3>;
+			queue-txready = <&qmgr 20>;
+			phy-mode = "rgmii";
+			phy-handle = <&phy8>;
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				phy8: ethernet-phy at 8 {
+					reg = <8>;
+				};
+			};
+		};
+	};
+};
-- 
2.31.1