[PATCH] ARM: dts: ixp4xx: Add Omicron device trees
Linus Walleij
linus.walleij at linaro.org
Mon Jul 19 05:21:49 PDT 2021
This coverts all the Omicron devices found in the Omicron boardfile
to device tree. The Omicron devices board file was added in 2011.
Cc: Richard Cochran <richardcochran at gmail.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Richard: it would be great if you can test this or at least
sanity check my DTS files so we can migrate the board files.
---
arch/arm/boot/dts/Makefile | 5 +-
.../boot/dts/intel-ixp42x-omicron-devixp.dts | 19 +++
.../boot/dts/intel-ixp42x-omicron-mic256.dts | 31 +++++
.../boot/dts/intel-ixp42x-omicron-miccpt.dts | 62 ++++++++++
arch/arm/boot/dts/intel-ixp42x-omicron.dtsi | 114 ++++++++++++++++++
5 files changed, 230 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/intel-ixp42x-omicron-devixp.dts
create mode 100644 arch/arm/boot/dts/intel-ixp42x-omicron-mic256.dts
create mode 100644 arch/arm/boot/dts/intel-ixp42x-omicron-miccpt.dts
create mode 100644 arch/arm/boot/dts/intel-ixp42x-omicron.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a8bd0ac4f8ae..1de207f19821 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -244,7 +244,10 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp42x-welltech-epbx100.dtb \
intel-ixp42x-iomega-nas100d.dtb \
intel-ixp42x-dlink-dsm-g600.dtb \
- intel-ixp43x-gateworks-gw2358.dtb
+ intel-ixp43x-gateworks-gw2358.dtb \
+ intel-ixp42x-omicron-devixp.dtb \
+ intel-ixp42x-omicron-miccpt.dtb \
+ intel-ixp42x-omicron-mic256.dtb
dtb-$(CONFIG_ARCH_KEYSTONE) += \
keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
diff --git a/arch/arm/boot/dts/intel-ixp42x-omicron-devixp.dts b/arch/arm/boot/dts/intel-ixp42x-omicron-devixp.dts
new file mode 100644
index 000000000000..bb984c3a5a38
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-omicron-devixp.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Omicron DEVIXP IXP425-based development board.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x-omicron.dtsi"
+
+/ {
+ model = "Omicron DEVIXP";
+ compatible = "omicron,devixp", "intel,ixp42x";
+
+ memory at 0 {
+ /* CHECKME: guessing 64 MB SDRAM */
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/intel-ixp42x-omicron-mic256.dts b/arch/arm/boot/dts/intel-ixp42x-omicron-mic256.dts
new file mode 100644
index 000000000000..cfde0b35c698
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-omicron-mic256.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Omicron MIC256 IXP425-based development board.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x-omicron.dtsi"
+
+/ {
+ model = "Omicron MIC256";
+ compatible = "omicron,mic256", "intel,ixp42x";
+
+ memory at 0 {
+ /* CHECKME: guessing 64 MB SDRAM */
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+
+ soc {
+ /* MIC256 has an addition 16MB of flash memory */
+ bus at 50000000 {
+ /* The second 16MB region at CS1 on the expansion bus */
+ flash at 51000000 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ reg = <0x51000000 0x1000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/intel-ixp42x-omicron-miccpt.dts b/arch/arm/boot/dts/intel-ixp42x-omicron-miccpt.dts
new file mode 100644
index 000000000000..6fbf4729f89b
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-omicron-miccpt.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Omicron MICCPT IXP425-based development board.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x-omicron.dtsi"
+
+/ {
+ model = "Omicron MICCPT";
+ compatible = "omicron,miccpt", "intel,ixp42x";
+
+ memory at 0 {
+ /* CHECKME: guessing 64 MB SDRAM */
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led-a {
+ /* CHECKME: no idea what color this really is */
+ label = "miccpt:red:a";
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ soc {
+ pci at c0000000 {
+ status = "ok";
+
+ /*
+ * Taken from NSLU2 PCI boardfile, INT A, B, C, D swizzled
+ * We have slots (IDSEL) 1, 2, 3 and 4.
+ */
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 1 3>, /* INT A on slot 1 is irq 1 */
+ <0x0800 0 0 2 &gpio0 2 3>, /* INT B on slot 1 is irq 2 */
+ <0x0800 0 0 3 &gpio0 3 3>, /* INT C on slot 1 is irq 3 */
+ <0x0800 0 0 4 &gpio0 4 3>, /* INT D on slot 1 is irq 4 */
+ /* IDSEL 2 */
+ <0x1000 0 0 1 &gpio0 2 3>, /* INT A on slot 2 is irq 2 */
+ <0x1000 0 0 2 &gpio0 3 3>, /* INT B on slot 2 is irq 3 */
+ <0x1000 0 0 3 &gpio0 4 3>, /* INT C on slot 2 is irq 4 */
+ <0x1000 0 0 4 &gpio0 1 3>, /* INT D on slot 2 is irq 1 */
+ /* IDSEL 3 */
+ <0x1800 0 0 1 &gpio0 3 3>, /* INT A on slot 3 is irq 3 */
+ <0x1800 0 0 2 &gpio0 4 3>, /* INT B on slot 3 is irq 4 */
+ <0x1800 0 0 3 &gpio0 1 3>, /* INT C on slot 3 is irq 1 */
+ <0x1800 0 0 4 &gpio0 2 3>, /* INT D on slot 3 is irq 2 */
+ /* IDSEL 4 */
+ <0x2000 0 0 1 &gpio0 4 3>, /* INT A on slot 3 is irq 4 */
+ <0x2000 0 0 2 &gpio0 1 3>, /* INT B on slot 3 is irq 2 */
+ <0x2000 0 0 3 &gpio0 2 3>, /* INT C on slot 3 is irq 2 */
+ <0x2000 0 0 4 &gpio0 3 3>; /* INT D on slot 3 is irq 3 */
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/intel-ixp42x-omicron.dtsi b/arch/arm/boot/dts/intel-ixp42x-omicron.dtsi
new file mode 100644
index 000000000000..ef959eb39179
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-omicron.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree include file for Intel IXP42x OMIXP platforms.
+ */
+
+#include "intel-ixp42x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory at 0 {
+ /* 64 MB SDRAM */
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+ stdout-path = "uart1:115200n8";
+ };
+
+ aliases {
+ /* These devices uses UART1 for default console */
+ serial0 = &uart1;
+ };
+
+ soc {
+ bus at 50000000 {
+ /* The first 16MB region at CS0 on the expansion bus */
+ flash at 0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+ * 16 MB of Flash in 128 0x20000 sized blocks
+ * mapped in at CS0.
+ */
+ reg = <0x00000000 0x1000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "Recovery Bootloader";
+ reg = <0 0x20000>;
+ read-only;
+ };
+ partition at 20000 {
+ label = "Calibration Data";
+ reg = <0x20000 0x20000>;
+ read-only;
+ };
+ partition at 40000 {
+ label = "Recovery FPGA";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ partition at 60000 {
+ label = "Release Bootloader";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+ partition at 80000 {
+ label = "Release FPGA";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+ partition at a0000 {
+ label = "Kernel";
+ reg = <0xa0000 0x160000>;
+ };
+ partition at 200000 {
+ label = "Filesystem";
+ reg = <0x200000 0x200000>;
+ };
+ partition at e00000 {
+ label = "Persistent Storage";
+ reg = <0xe00000 0x200000>;
+ };
+ };
+ };
+
+ /* EthB */
+ ethernet at c8009000 {
+ status = "ok";
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ /* EthC */
+ ethernet at c800a000 {
+ status = "ok";
+ queue-rx = <&qmgr 4>;
+ queue-txready = <&qmgr 21>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+ };
+};
--
2.31.1
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