[EXT] Re: The problem about arm64: io: Relax implicit barriers in default I/O accessors

[Frank Li]

> -----Original Message-----
> From: Will Deacon <will at kernel.org>
> Sent: Tuesday, July 6, 2021 12:11 PM
> To: Frank Li <frank.li at nxp.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>; Zhi Li <lznuaa at gmail.com>;
> Shenwei Wang <shenwei.wang at nxp.com>; Han Xu <han.xu at nxp.com>; Nitin Garg
> <nitin.garg at nxp.com>; Jason Liu <jason.hui.liu at nxp.com>; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [EXT] Re: The problem about arm64: io: Relax implicit barriers
> in default I/O accessors
> 
> Caution: EXT Email
> 
> Hi Frank,
> 
> On Wed, Jun 23, 2021 at 03:48:10PM +0000, Frank Li wrote:
> > > I think you had a support case open with Arm [1] which I'm not able to
> > > access -- please can you ask them about the two examples above?
> >
> > Still not get feedback from ARM.
> 
> Just wondering if you were able to solve this without the need to change
> Linux?

Sorry for late reply

For CCI-500 and 550, ARM removed support for barrier transactions but CCI-400 supports barrier transactions. With CCI-400 it is a valid configuration to have SYSBARDISABLE LOW in Cortex-A processors. This change in Linux kernel is assuming that the SYSBARDISABLE is set to HIGH hence its not correct change for all products having various versions of ARM CCI IP.

Frank Li

> 
> Cheers,
> 
> Will