[EXT] Re: [PATCH] clocksource: Add Marvell Errata-38627 workaround

[Marc Zyngier]

Hi Bharat,

On Tue, 13 Jul 2021 03:40:22 +0100,
Bharat Bhushan <bbhushan2 at marvell.com> wrote:
> 
> Hi Mark,
>
> -----Original Message-----
> From: Mark Rutland <mark.rutland at arm.com>

[...]

> > From your description so far, this doesn't sound like it is
> > specific to the timer interrupt. Is it possible for a different
> > interrupt to trigger this, e.g:
> > 
> > * Can the same happen with another PPI, e.g. the PMU interrupt if that
> >   gets de-asserted, or there's a race with DAIF.I?
> > 
> > * Can the same happen with an SGI, e.g. if one CPU asserts then
> >   de-asserts an SGI targetting another CPU, or there's a race with
> >   DAIF.I?
> > 
> > * Can the same happen with an SPI, e.g. if a device asserts then
> >   de-asserts its IRQ line, or there's a race with DAIF.I?
> 
> No issue with edge triggered, but this can happen with any level
> sensitive interrupt.

So let's say CPU0 is targeted by a level-triggered SPI, and right when
the interrupt is reaching the CPU interface, CPU1 disables this
interrupt, which gets recalled, and CPU0 never takes the interrupt.
Bug hits again. Drivers do that.

I actually suspect that an edge-triggered interrupt would result in
the same issue, unless your GIC implementation isn't able to perform a
recall on edge interrupts.

I don't understand why you are only considering the timer here. Any
interrupt can trigger this, and if there is going to be a workaround,
it will need to be robust against all interrupts being retired, no
matter what device triggers it.

And given that the OoO nature of the machine leaks non architectural
state, potentially belonging to a different security context, this
isn't something that should be taken lightly.

	M.

-- 
Without deviation from the norm, progress is not possible.