[PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
CK Hu
ck.hu at mediatek.com
Tue Jul 6 21:44:21 PDT 2021
Hi, Jason:
On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> 1. Add mtk-mmsys support for mt8195 vodsys0.
> 2. Change the clock driver of vdosys0 is probed
> from the probe of mtk-mmsys.
Move clock driver part out of this patch. And ask chun-jie to squash
clock driver modification to his patch [1].
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210616224743.5109-16-chun-jie.chen@mediatek.com/
Regards,
CK
>
> Signed-off-by: jason-jh.lin <jason-jh.lin at mediatek.com>
> ---
> drivers/clk/mediatek/clk-mt8195-vdo0.c | 24 ++--
> drivers/soc/mediatek/mt8195-mmsys.h | 173 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 ++
> 3 files changed, 198 insertions(+), 10 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> index 8e23f267a1e6..940be5377f70 100644
> --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c
> +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> @@ -94,20 +94,24 @@ static const struct mtk_clk_desc vdo0_desc = {
> .num_clks = ARRAY_SIZE(vdo0_clks),
> };
>
> -static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
> - {
> - .compatible = "mediatek,mt8195-vdosys0",
> - .data = &vdo0_desc,
> - }, {
> - /* sentinel */
> - }
> -};
> +static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_onecell_data *clk_data;
> +
> + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(vdo0_clks));
> +
> + mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
>
> static struct platform_driver clk_mt8195_vdo0_drv = {
> - .probe = mtk_clk_simple_probe,
> + .probe = clk_mt8195_vdo0_probe,
> .driver = {
> .name = "clk-mt8195-vdo0",
> - .of_match_table = of_match_clk_mt8195_vdo0,
> },
> };
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..47f3d0ea3c6c
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,173 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
> +#define MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
> +#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
> +#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
> +#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
> +#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
> +#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
> +#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12)
> +#define SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
> +#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
> +#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
> +#define SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
> +#define SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
> +#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
> +#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
> +#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
> +#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
> +#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
> +#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT 0xf38
> +#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
> +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
> +#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
> +#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
> +#define SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
> +#define SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
> +#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
> +#define SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
> +#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
> +#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
> +#define SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11)
> +#define SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
> +#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
> +#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
> +#define SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
> +
> +#define MT8195_VDO1_VPP3_ASYNC_SOUT 0xf54
> +#define SOUT_TO_VPP_MERGE0_P0_SEL (0 << 0)
> +#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
> +
> +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> +#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> +#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> +#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> +#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> +#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
> +#define MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
> +#define MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
> +#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> +#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> +#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
> +#define MERGE4_SOUT_TO_DPI0_SEL (1 << 0)
> +#define MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
> +#define MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2 (0 << 0)
> +#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3 (0 << 0)
> +#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
> +#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT (0 << 0)
> +#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
> +#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0 (0 << 0)
> +#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
> +#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1 (0 << 0)
> +#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
> +#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0 (0 << 0)
> +#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
> +#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1 (0 << 0)
> +#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> +#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT (1 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT (2 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR (3 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR (4 << 0)
> +
> +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
> +#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0 (0 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT (2 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT (3 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT (4 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT (5 << 0)
> +
> +#define MT8195_VDO1_DISP_DPI0_SEL_IN 0xf0c
> +#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> +#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> +#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 080660ef11bf..1fb241750897 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -13,6 +13,7 @@
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> #include "mt8183-mmsys.h"
> +#include "mt8195-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> @@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys0",
> + .data = &mt8195_vdosys0_driver_data,
> + },
> { }
> };
>
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