[PATCH 1/2] soc: imx: gpcv2: Turn domain->pgc into bitfield

[Marek Vasut]

On 7/2/21 7:02 PM, Lucas Stach wrote:
> Am Donnerstag, dem 01.07.2021 um 01:01 +0200 schrieb Marek Vasut:
>> There is currently the MX8MM GPU domain, which is in fact a composite domain
>> for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
>> to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
>> time. This is currently not possible.
>>
>> Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
>> iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
>> register array. This way it is possible to configure all GPC_PGC_nCTRL
>> registers required in a particular domain.
>>
>> This is a preparatory patch, no functional change.
> 
> Which tree was used to generate this patch? This does not apply on top
> of next or Shawn's imx/drivers tree and from a glance is at least
> missing the 8MN power domains.

Next with this additional patch
[PATCH] soc: imx: gpcv2: Assert reset before ungating clock