[PATCH v1 2/2] arm64: dts: mt6779: Support ufshci and ufsphy

[Matthias Brugger]

On 23/12/2020 05:13, Stanley Chu wrote:
> Support UFS on MT6779 platforms by adding ufshci and ufsphy
> nodes in dts file.
> 
> Reviewed-by: Hanks Chen <hanks.chen at mediatek.com>
> Signed-off-by: Stanley Chu <stanley.chu at mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt6779.dtsi | 36 +++++++++++++++++++++++-
>  1 file changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..a8584b00cc9d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -225,6 +225,41 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		ufshci: ufshci at 11270000 {
> +			compatible = "mediatek,mt8183-ufshci";
> +			reg = <0 0x11270000 0 0x2300>;
> +			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW 0>;
> +			phys = <&ufsphy>;
> +
> +			clocks = <&infracfg_ao CLK_INFRA_UFS>,
> +				 <&infracfg_ao CLK_INFRA_UFS_TICK>,
> +				 <&infracfg_ao CLK_INFRA_UFS_AXI>,
> +				 <&infracfg_ao CLK_INFRA_UNIPRO_TICK>,
> +				 <&infracfg_ao CLK_INFRA_UNIPRO_MBIST>,
> +				 <&topckgen CLK_TOP_FAES_UFSFDE>,
> +				 <&infracfg_ao CLK_INFRA_AES_UFSFDE>,
> +				 <&infracfg_ao CLK_INFRA_AES_BCLK>;
> +			clock-names = "ufs", "ufs_tick", "ufs_axi",
> +				      "unipro_tick", "unipro_mbist",
> +				      "aes_top", "aes_infra", "aes_bclk";
> +			freq-table-hz = <0 0>, <0 0>, <0 0>,
> +					<0 0>, <0 0>, <0 0>,
> +					<0 0>, <0 0>;

We are missing required property: vcc-supply

> +
> +			mediatek,ufs-disable-ah8;
> +			mediatek,ufs-support-va09;

Although supported in the driver, these are not defined in the binding document
(ufs-mediatek.txt). Before adding them, it would be good if you could update the
description to use yaml syntax instead.

Please also add "mediatek,ufs-boost-crypt" which is not defined in the binding
neither.

Regards,
Matthias

> +		};
> +
> +		ufsphy: phy at 11fa0000 {
> +			compatible = "mediatek,mt8183-ufsphy";
> +			reg = <0 0x11fa0000 0 0xc000>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&infracfg_ao CLK_INFRA_UNIPRO_SCK>,
> +				 <&infracfg_ao CLK_INFRA_UFS_MP_SAP_BCLK>;
> +			clock-names = "unipro", "mp";
> +		};
> +
>  		mfgcfg: clock-controller at 13fbf000 {
>  			compatible = "mediatek,mt6779-mfgcfg", "syscon";
>  			reg = <0 0x13fbf000 0 0x1000>;
> @@ -266,6 +301,5 @@
>  			reg = <0 0x1b000000 0 0x1000>;
>  			#clock-cells = <1>;
>  		};
> -
>  	};
>  };
>