[PATCH v3 3/5] arm64: dts: ti: Add support for AM642 SoC
Suman Anna
s-anna at ti.com
Mon Jan 25 18:02:27 EST 2021
On 1/25/21 4:48 PM, Suman Anna wrote:
> Hi Dave,
>
> On 1/20/21 2:25 PM, Dave Gerlach wrote:
>> The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
>> providing advanced system integration to enable applications such as
>> Motor Drives, PLC, Remote IO and IoT Gateways.
>>
>> Some highlights of this SoC are:
>> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
>> MCUs, and a single Cortex-M4F.
>> * Two Gigabit Industrial Communication Subsystems (ICSSG).
>> * Integrated Ethernet switch supporting up to a total of two external
>> ports.
>> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
>> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
>> peripherals.
>> * Centralized System Controller for Security, Power, and Resource
>> Management (DMSC).
>>
>> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
>> for further details: https://www.ti.com/lit/pdf/spruim2
>>
>> Introduce basic support for the AM642 SoC to enable ramdisk or MMC
>> boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals
>> under cbass_main and the i2c, spi, and uart MCU domain periperhals
>> under cbass_mcu.
>>
>> Signed-off-by: Faiz Abbas <faiz_abbas at ti.com>
>> Signed-off-by: Aswath Govindraju <a-govindraju at ti.com>
>> Signed-off-by: Dave Gerlach <d-gerlach at ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 332 +++++++++++++++++++++++
>> arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++++
>> arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++++
>> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++
>> 4 files changed, 576 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> new file mode 100644
>> index 000000000000..e3ef4bff04af
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> @@ -0,0 +1,332 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device Tree Source for AM642 SoC Family Main Domain peripherals
>> + *
>> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +&cbass_main {
>> + oc_sram: sram at 70000000 {
>> + compatible = "mmio-sram";
>> + reg = <0x00 0x70000000 0x00 0x200000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x00 0x70000000 0x200000>;
>> +
>> + atf-sram at 0 {
>> + reg = <0x0 0x1a000>;
>> + };
>> + };
>> +
>> + gic500: interrupt-controller at 1800000 {
>> + compatible = "arm,gic-v3";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
>> + <0x00 0x01840000 0x00 0xC0000>; /* GICR */
>> + /*
>> + * vcpumntirq:
>> + * virtual CPU interface maintenance interrupt
>> + */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + gic_its: msi-controller at 1820000 {
>> + compatible = "arm,gic-v3-its";
>> + reg = <0x00 0x01820000 0x00 0x10000>;
>> + socionext,synquacer-pre-its = <0x1000000 0x400000>;
>> + msi-controller;
>> + #msi-cells = <1>;
>> + };
>> + };
>> +
>> + dmss: dmss {
>> + compatible = "simple-mfd";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + dma-ranges;
>> + ranges;
>> +
>> + secure_proxy_main: mailbox at 4d000000 {
>> + compatible = "ti,am654-secure-proxy";
>> + #mbox-cells = <1>;
>> + reg-names = "target_data", "rt", "scfg";
>> + reg = <0x00 0x4d000000 0x00 0x80000>,
>> + <0x00 0x4a600000 0x00 0x80000>,
>> + <0x00 0x4a400000 0x00 0x80000>;
>> + interrupt-names = "rx_012";
>> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +
>> + dmsc: dmsc at 44043000 {
>> + compatible = "ti,k2g-sci";
>> + ti,host-id = <12>;
>> + mbox-names = "rx", "tx";
>> + mboxes= <&secure_proxy_main 12>,
>> + <&secure_proxy_main 13>;
>> + reg-names = "debug_messages";
>> + reg = <0x00 0x44043000 0x00 0xfe0>;
>> +
>> + k3_pds: power-controller {
>> + compatible = "ti,sci-pm-domain";
>> + #power-domain-cells = <2>;
>> + };
>> +
>> + k3_clks: clocks {
>> + compatible = "ti,k2g-sci-clk";
>> + #clock-cells = <2>;
>> + };
>> +
>> + k3_reset: reset-controller {
>> + compatible = "ti,sci-reset";
>> + #reset-cells = <2>;
>> + };
>> + };
>> +
>> + main_pmx0: pinctrl at f4000 {
>> + compatible = "pinctrl-single";
>> + reg = <0x00 0xf4000 0x00 0x2d0>;
>
> Hmm, should the size be 0x2d8? I see the TRM defines a PADMMD_PADCONFIG181
> register at 0xf42d4.
Please ignore, learnt that this is a bug in the current version of TRM.
regards
Suman
>
>> + #pinctrl-cells = <1>;
>> + pinctrl-single,register-width = <32>;
>> + pinctrl-single,function-mask = <0xffffffff>;
>> + };
>> +
>> + main_conf: syscon at 43000000 {
>> + compatible = "syscon", "simple-mfd";
>> + reg = <0x00 0x43000000 0x00 0x20000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x00 0x00 0x43000000 0x20000>;
>> +
>> + chipid at 14 {
>> + compatible = "ti,am654-chipid";
>> + reg = <0x00000014 0x4>;
>> + };
>> + };
>> +
>> + main_uart0: serial at 2800000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x02800000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 146 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + main_uart1: serial at 2810000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x02810000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 152 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + main_uart2: serial at 2820000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x02820000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 153 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + main_uart3: serial at 2830000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x02830000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 154 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + main_uart4: serial at 2840000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x02840000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 155 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + main_uart5: serial at 2850000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x02850000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 156 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + main_uart6: serial at 2860000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x02860000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 158 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + main_i2c0: i2c at 20000000 {
>> + compatible = "ti,am64-i2c", "ti,omap4-i2c";
>> + reg = <0x00 0x20000000 0x00 0x100>;
>> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 102 2>;
>> + clock-names = "fck";
>> + };
>> +
>> + main_i2c1: i2c at 20010000 {
>> + compatible = "ti,am64-i2c", "ti,omap4-i2c";
>> + reg = <0x00 0x20010000 0x00 0x100>;
>> + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 103 2>;
>> + clock-names = "fck";
>> + };
>> +
>> + main_i2c2: i2c at 20020000 {
>> + compatible = "ti,am64-i2c", "ti,omap4-i2c";
>> + reg = <0x00 0x20020000 0x00 0x100>;
>> + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 104 2>;
>> + clock-names = "fck";
>> + };
>> +
>> + main_i2c3: i2c at 20030000 {
>> + compatible = "ti,am64-i2c", "ti,omap4-i2c";
>> + reg = <0x00 0x20030000 0x00 0x100>;
>> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 105 2>;
>> + clock-names = "fck";
>> + };
>> +
>> + main_spi0: spi at 20100000 {
>> + compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
>> + reg = <0x00 0x20100000 0x00 0x400>;
>> + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 141 0>;
>> + dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
>> + dma-names = "tx0", "rx0";
>> + };
>> +
>> + main_spi1: spi at 20110000 {
>> + compatible = "ti,am654-mcspi","ti,omap4-mcspi";
>> + reg = <0x00 0x20110000 0x00 0x400>;
>> + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 142 0>;
>> + };
>> +
>> + main_spi2: spi at 20120000 {
>> + compatible = "ti,am654-mcspi","ti,omap4-mcspi";
>> + reg = <0x00 0x20120000 0x00 0x400>;
>> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 143 0>;
>> + };
>> +
>> + main_spi3: spi at 20130000 {
>> + compatible = "ti,am654-mcspi","ti,omap4-mcspi";
>> + reg = <0x00 0x20130000 0x00 0x400>;
>> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 144 0>;
>> + };
>> +
>> + main_spi4: spi at 20140000 {
>> + compatible = "ti,am654-mcspi","ti,omap4-mcspi";
>> + reg = <0x00 0x20140000 0x00 0x400>;
>> + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 145 0>;
>> + };
>> +
>> + sdhci0: mmc at fa10000 {
>> + compatible = "ti,am64-sdhci-8bit";
>> + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
>> + clock-names = "clk_ahb", "clk_xin";
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + mmc-hs400-1_8v;
>> + ti,trm-icp = <0x2>;
>> + ti,otap-del-sel-legacy = <0x0>;
>> + ti,otap-del-sel-mmc-hs = <0x0>;
>> + ti,otap-del-sel-ddr52 = <0x6>;
>> + ti,otap-del-sel-hs200 = <0x7>;
>> + ti,otap-del-sel-hs400 = <0x4>;
>> + };
>> +
>> + sdhci1: mmc at fa00000 {
>> + compatible = "ti,am64-sdhci-4bit";
>> + reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
>> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
>> + clock-names = "clk_ahb", "clk_xin";
>> + ti,trm-icp = <0x2>;
>> + ti,otap-del-sel-legacy = <0x0>;
>> + ti,otap-del-sel-sd-hs = <0xf>;
>> + ti,otap-del-sel-sdr12 = <0xf>;
>> + ti,otap-del-sel-sdr25 = <0xf>;
>> + ti,otap-del-sel-sdr50 = <0xc>;
>> + ti,otap-del-sel-sdr104 = <0x6>;
>> + ti,otap-del-sel-ddr50 = <0x9>;
>> + ti,clkbuf-sel = <0x7>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
>> new file mode 100644
>> index 000000000000..1d2be485a669
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
>> @@ -0,0 +1,76 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device Tree Source for AM64 SoC Family MCU Domain peripherals
>> + *
>> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +&cbass_mcu {
>> + mcu_uart0: serial at 4a00000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x04a00000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 149 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + mcu_uart1: serial at 4a10000 {
>> + compatible = "ti,am64-uart", "ti,am654-uart";
>> + reg = <0x00 0x04a10000 0x00 0x100>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-frequency = <48000000>;
>> + current-speed = <115200>;
>> + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 160 0>;
>> + clock-names = "fclk";
>> + };
>> +
>> + mcu_i2c0: i2c at 4900000 {
>> + compatible = "ti,am64-i2c", "ti,omap4-i2c";
>> + reg = <0x00 0x04900000 0x00 0x100>;
>> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 106 2>;
>> + clock-names = "fck";
>> + };
>> +
>> + mcu_i2c1: i2c at 4910000 {
>> + compatible = "ti,am64-i2c", "ti,omap4-i2c";
>> + reg = <0x00 0x04910000 0x00 0x100>;
>> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 107 2>;
>> + clock-names = "fck";
>> + };
>> +
>> + mcu_spi0: spi at 4b00000 {
>> + compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
>> + reg = <0x00 0x04b00000 0x00 0x400>;
>> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 147 0>;
>> + };
>> +
>> + mcu_spi1: spi at 4b10000 {
>> + compatible = "ti,am654-mcspi","ti,omap4-mcspi";
>> + reg = <0x00 0x04b10000 0x00 0x400>;
>> + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 148 0>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
>> new file mode 100644
>> index 000000000000..0ae8c844c482
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
>> @@ -0,0 +1,103 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device Tree Source for AM642 SoC Family
>> + *
>> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/pinctrl/k3.h>
>> +#include <dt-bindings/soc/ti,sci_pm_domain.h>
>> +
>> +/ {
>> + model = "Texas Instruments K3 AM642 SoC";
>> + compatible = "ti,am642";
>> + interrupt-parent = <&gic500>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + aliases {
>> + serial0 = &mcu_uart0;
>> + serial1 = &mcu_uart1;
>> + serial2 = &main_uart0;
>> + serial3 = &main_uart1;
>> + serial4 = &main_uart2;
>> + serial5 = &main_uart3;
>> + serial6 = &main_uart4;
>> + serial7 = &main_uart5;
>> + serial8 = &main_uart6;
>> + };
>> +
>> + chosen { };
>> +
>> + firmware {
>> + optee {
>> + compatible = "linaro,optee-tz";
>> + method = "smc";
>> + };
>> +
>> + psci: psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> + };
>> + };
>> +
>> + a53_timer0: timer-cl0-cpu0 {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
>> + };
>> +
>> + pmu: pmu {
>> + compatible = "arm,cortex-a53-pmu";
>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + cbass_main: bus at f4000 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
>
> Follows the above..
>
> regards
> Suman
>
>> + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
>> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
>> + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
>> + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
>> + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
>> + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
>> + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
>> + <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
>> + <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
>> + <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
>> + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
>> + <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
>> + <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
>> + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
>> + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
>> + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
>> + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
>> + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
>> + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
>> + <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
>> + <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
>> + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
>> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
>> +
>> + /* MCU Domain Range */
>> + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
>> +
>> + cbass_mcu: bus at 4000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
>> + };
>> + };
>> +};
>> +
>> +/* Now include the peripherals for each bus segments */
>> +#include "k3-am64-main.dtsi"
>> +#include "k3-am64-mcu.dtsi"
>> diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
>> new file mode 100644
>> index 000000000000..e2b397c88401
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
>> @@ -0,0 +1,65 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device Tree Source for AM642 SoC family in Dual core configuration
>> + *
>> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "k3-am64.dtsi"
>> +
>> +/ {
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu-map {
>> + cluster0: cluster0 {
>> + core0 {
>> + cpu = <&cpu0>;
>> + };
>> +
>> + core1 {
>> + cpu = <&cpu1>;
>> + };
>> + };
>> + };
>> +
>> + cpu0: cpu at 0 {
>> + compatible = "arm,cortex-a53";
>> + reg = <0x000>;
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&L2_0>;
>> + };
>> +
>> + cpu1: cpu at 1 {
>> + compatible = "arm,cortex-a53";
>> + reg = <0x001>;
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&L2_0>;
>> + };
>> + };
>> +
>> + L2_0: l2-cache0 {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-size = <0x40000>;
>> + cache-line-size = <64>;
>> + cache-sets = <512>;
>> + };
>> +};
>>
>
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