[RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

[Will Deacon]

On Thu, Jan 21, 2021 at 04:25:54PM +0000, Marc Zyngier wrote:
> On 2021-01-21 15:12, Mohamed Mediouni wrote:
> > Please ignore that patch.
> > 
> > It turns out that the PCIe controller on Apple M1 expects posted
> > writes and so the memory range for it ought to be set nGnRE.
> > So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs.
> > 
> > The MAIR approach isn’t adequate for such a thing, so we’ll have to
> > look elsewhere.
> 
> Well, there isn't many alternative to having a memory type defined
> in MAIR if you want to access your PCIe devices with specific
> semantics.
> 
> It probably means defining a memory type for PCI only, but:
> - we only have a single free MT entry, and I'm not sure we can
>   afford to waste this on a specific platform (can we re-purpose
>   GRE instead?),

We already have an nGnRnE MAIR for config space accesses.

Will