[linux-sunxi] Re: [PATCH v3 02/21] mmc: sunxi: add support for A100 mmc controller

[Chen-Yu Tsai]

On Mon, Jan 18, 2021 at 11:53 PM Andre Przywara <andre.przywara at arm.com> wrote:
>
> On Mon, 18 Jan 2021 14:28:54 +0100
> Maxime Ripard <maxime at cerno.tech> wrote:
>
> Hi Maxime,
>
> > On Mon, Jan 18, 2021 at 02:08:29AM +0000, Andre Przywara wrote:
> > > From: Yangtao Li <frank at allwinnertech.com>
> > >
> > > This patch adds support for A100 MMC controller, which use word
> > > address for internal dma.
> > >
> > > Signed-off-by: Yangtao Li <frank at allwinnertech.com>
> > > Signed-off-by: Andre Przywara <andre.przywara at arm.com>
> >
> > We should also disable the timings setup in probe to derive them from
> > the DT. This is causing issues on some SoCs already, so it would be
> > best to not make the situation worse
>
> But only for those new SoCs, where we have the speed modes in the DT
> in every case (so only new ones)? And this disabling would be
> SoC/compatible string dependent? Happy to send a patch later if that is
> what you were thinking about.
>
> Also I was wondering about the voltage dependent speed modes: At the
> moment the driver declares both MMC_CAP_1_8V_DDR and MMC_CAP_3_3V_DDR,
> so I mimic this in the .dtsi. However in the eventual DTB this looks
> somewhat dodgy, since most boards only support one of those voltages. Do
> we ignore this, and rely on the vqmmc-supply to limit this choice?

IIRC the DDR flags for separate voltages was added after we (I) added
MMC DDR support to our driver.

And yes, the core also checks vqmmc-supply before actually selecting
the mode.

ChenYu

> Cheers,
> Andre
>
> Btw: This patch is already in Ulf's -next tree, I just included it here
> for the sake of completeness. Is that a problem? I don't think it
> affects the build, so we don't care too much?
>
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