[PATCH v2 4/4] ARM: imx7: add support for iotmaxx gateway

[Fabio Estevam]

Hi Steffen,

On Tue, Jul 14, 2020 at 2:12 AM Steffen Trumtrar
<s.trumtrar at pengutronix.de> wrote:

> +       memory {

memory at 80000000 to avoid dtc W=1 warning.

> +&ecspi2 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_ecspi2>;
> +       num-chipselects = <1>;

This property is not used for spi-imx.

> +       status = "okay";
> +
> +       flash: m25p80 at 0 {

Node names should be generic:

spi-flash at 0

> +/* Expansion slot */
> +&ecspi3 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_ecspi3>;
> +       num-chipselects = <1>;
> +       status = "okay";
> +};
> +
> +&fec2 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_enet2>,
> +                   <&pinctrl_mdio>,
> +                   <&pinctrl_rmii_phy>;
> +       /* set the enet_ref_clk and enet_out with a 50MHz clock */
> +       assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
> +       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
> +       assigned-clock-rates = <50000000>;
> +       clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
> +                <&clks IMX7D_ENET_AXI_ROOT_CLK>,
> +                <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
> +                <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>,
> +                <&clks IMX7D_ENET2_REF_ROOT_DIV>;
> +       clock-names = "ipg", "ahb", "ptp",
> +                     "enet_clk_ref", "enet_out";
> +       phy-handle = <&ethphy1>;
> +       phy-mode = "rmii";
> +       phy-reset-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;

This property is considered obsolete.

Please describe the Ethernet PHY reset inside the ethernet-phy nodes as per:
Documentation/devicetree/bindings/net/ethernet-phy.yaml

> +       pcf85363: pcf85363 at 51 {

rtc at 51