[PATCH v3 02/13] arm: dts: owl-s500: Set CMU clocks for UARTs

[Matheus Castello]

Em 12/29/2020 6:17 PM, Cristian Ciocaltea escreveu:
> Set Clock Management Unit clocks for the UART nodes of Actions Semi
> S500 SoCs and remove the dummy "uart2_clk" and "uart3_clk" fixed clocks.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at gmail.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>
> ---
> Changes in v3:
>   - Added Reviewed-by from Mani
>   - Removed the dummy 'uart2_clk' and 'uart3_clk' nodes from all owl-s500 DTS,
>     per Mani's review
> 
>   arch/arm/boot/dts/owl-s500-cubieboard6.dts     | 7 -------
>   arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 -------
>   arch/arm/boot/dts/owl-s500-labrador-base-m.dts | 7 -------
>   arch/arm/boot/dts/owl-s500-roseapplepi.dts     | 7 -------
>   arch/arm/boot/dts/owl-s500-sparky.dts          | 7 -------
>   arch/arm/boot/dts/owl-s500.dtsi                | 7 +++++++
>   6 files changed, 7 insertions(+), 35 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts
> index 7c96c59b610d..c2b02895910c 100644
> --- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts
> +++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts
> @@ -25,12 +25,6 @@ memory at 0 {
>   		device_type = "memory";
>   		reg = <0x0 0x80000000>;
>   	};
> -
> -	uart3_clk: uart3-clk {
> -		compatible = "fixed-clock";
> -		clock-frequency = <921600>;
> -		#clock-cells = <0>;
> -	};
>   };
>   
>   &timer {
> @@ -39,5 +33,4 @@ &timer {
>   
>   &uart3 {
>   	status = "okay";
> -	clocks = <&uart3_clk>;
>   };
> diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
> index e610d49395d2..7ae34a23e320 100644
> --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
> +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
> @@ -18,15 +18,8 @@ aliases {
>   	chosen {
>   		stdout-path = "serial3:115200n8";
>   	};
> -
> -	uart3_clk: uart3-clk {
> -		compatible = "fixed-clock";
> -		clock-frequency = <921600>;
> -		#clock-cells = <0>;
> -	};
>   };
>   
>   &uart3 {
>   	status = "okay";
> -	clocks = <&uart3_clk>;
>   };
> diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
> index c92f8bdcb331..1585e33f703b 100644
> --- a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
> +++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
> @@ -21,15 +21,8 @@ aliases {
>   	chosen {
>   		stdout-path = "serial3:115200n8";
>   	};
> -
> -	uart3_clk: uart3-clk {
> -		compatible = "fixed-clock";
> -		clock-frequency = <921600>;
> -		#clock-cells = <0>;
> -	};
>   };
>   
>   &uart3 {
>   	status = "okay";
> -	clocks = <&uart3_clk>;
>   };
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> index a2087e617cb2..800edf5d2d12 100644
> --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -25,12 +25,6 @@ memory at 0 {
>   		device_type = "memory";
>   		reg = <0x0 0x80000000>; /* 2GB */
>   	};
> -
> -	uart2_clk: uart2-clk {
> -		compatible = "fixed-clock";
> -		clock-frequency = <921600>;
> -		#clock-cells = <0>;
> -	};
>   };
>   
>   &twd_timer {
> @@ -43,5 +37,4 @@ &timer {
>   
>   &uart2 {
>   	status = "okay";
> -	clocks = <&uart2_clk>;
>   };
> diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts
> index c665ce8b88b4..9d8f7336bec0 100644
> --- a/arch/arm/boot/dts/owl-s500-sparky.dts
> +++ b/arch/arm/boot/dts/owl-s500-sparky.dts
> @@ -25,12 +25,6 @@ memory at 0 {
>   		device_type = "memory";
>   		reg = <0x0 0x40000000>; /* 1 or 2 GiB */
>   	};
> -
> -	uart3_clk: uart3-clk {
> -		compatible = "fixed-clock";
> -		clock-frequency = <921600>;
> -		#clock-cells = <0>;
> -	};
>   };
>   
>   &timer {
> @@ -39,5 +33,4 @@ &timer {
>   
>   &uart3 {
>   	status = "okay";
> -	clocks = <&uart3_clk>;
>   };
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 5d5ad9db549b..ac3d04c75dd5 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -131,6 +131,7 @@ uart0: serial at b0120000 {
>   			compatible = "actions,s500-uart", "actions,owl-uart";
>   			reg = <0xb0120000 0x2000>;
>   			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART0>;
>   			status = "disabled";
>   		};
>   
> @@ -138,6 +139,7 @@ uart1: serial at b0122000 {
>   			compatible = "actions,s500-uart", "actions,owl-uart";
>   			reg = <0xb0122000 0x2000>;
>   			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART1>;
>   			status = "disabled";
>   		};
>   
> @@ -145,6 +147,7 @@ uart2: serial at b0124000 {
>   			compatible = "actions,s500-uart", "actions,owl-uart";
>   			reg = <0xb0124000 0x2000>;
>   			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART2>;
>   			status = "disabled";
>   		};
>   
> @@ -152,6 +155,7 @@ uart3: serial at b0126000 {
>   			compatible = "actions,s500-uart", "actions,owl-uart";
>   			reg = <0xb0126000 0x2000>;
>   			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART3>;
>   			status = "disabled";
>   		};
>   
> @@ -159,6 +163,7 @@ uart4: serial at b0128000 {
>   			compatible = "actions,s500-uart", "actions,owl-uart";
>   			reg = <0xb0128000 0x2000>;
>   			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART4>;
>   			status = "disabled";
>   		};
>   
> @@ -166,6 +171,7 @@ uart5: serial at b012a000 {
>   			compatible = "actions,s500-uart", "actions,owl-uart";
>   			reg = <0xb012a000 0x2000>;
>   			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART5>;
>   			status = "disabled";
>   		};
>   
> @@ -173,6 +179,7 @@ uart6: serial at b012c000 {
>   			compatible = "actions,s500-uart", "actions,owl-uart";
>   			reg = <0xb012c000 0x2000>;
>   			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cmu CLK_UART6>;
>   			status = "disabled";
>   		};
>   
> 

Tested-by: Matheus Castello <matheus at castello.eng.br>