[PATCH] clk: sunxi-ng: h6: Fix CEC clock

Maxime Ripard maxime at cerno.tech
Wed Jan 6 11:51:36 EST 2021


On Wed, Jan 06, 2021 at 02:32:46PM +0000, Andre Przywara wrote:
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use the right
> flag to actually activate that.
> 
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Reported-by: Jernej Skrabec <jernej.skrabec at siol.net>
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>

Applied, thanks!
Maxime
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