[PATCH 1/3] clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL

[Jerome Brunet]

On Sat 26 Dec 2020 at 13:15, Martin Blumenstingl <martin.blumenstingl at googlemail.com> wrote:

> The "rate" parameter in meson_clk_pll_set_rate() contains the new rate.
> Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try
> to switch from the new rate to the same ratte again.

Small typo above fixed while applying


>
> Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> ---
>  drivers/clk/meson/clk-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> index b17a13e9337c..9404609b5ebf 100644
> --- a/drivers/clk/meson/clk-pll.c
> +++ b/drivers/clk/meson/clk-pll.c
> @@ -371,7 +371,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>  	if (parent_rate == 0 || rate == 0)
>  		return -EINVAL;
>  
> -	old_rate = rate;
> +	old_rate = clk_hw_get_rate(hw);
>  
>  	ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
>  	if (ret)