[PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output
maxime at cerno.tech
Thu Feb 18 02:58:35 EST 2021
On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
> Previously the variable rate audio pll output was fixed to a divider of
> four. This is unfortunately incompatible with generating commonly used
> I2S core clock rates like 24.576MHz from the 24MHz parent clock.
> This commit adds support for arbitrary audio pll output dividers to fix
> Signed-off-by: Tobias Schramm <t.schramm at manjaro.org>
It's not really clear to me how that would help.
The closest frequency we can provide for 24.576MHz would be 24580645 Hz,
with N = 127, M = 31 and P = 4, so it would work with what we have
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