[PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable

Stephen Boyd sboyd at kernel.org
Mon Feb 8 21:32:36 EST 2021

Quoting Michael Tretter (2021-01-20 23:16:50)
> The disabling of the PLL is not fully implemented, because according to
> the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to
> be set to bring the PLL into reset.
> Set the bits to disable the PLL.
> Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
> Acked-by: Michal Simek <michal.simek at xilinx.com>
> ---

Applied to clk-next

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