[v4] PCI: Avoid unsync of LTR mechanism configuration

Mika Westerberg mika.westerberg at linux.intel.com
Thu Feb 4 05:00:21 EST 2021

On Thu, Feb 04, 2021 at 05:51:25PM +0800, mingchuang.qiao at mediatek.com wrote:
> From: Mingchuang Qiao <mingchuang.qiao at mediatek.com>
> In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is
> configured in pci_configure_ltr(). If device and bridge both support LTR
> mechanism, the "LTR Mechanism Enable" bit of device and bridge will be
> enabled in DEVCTL2 register. And pci_dev->ltr_path will be set as 1.
> If PCIe link goes down when device resets, the "LTR Mechanism Enable" bit
> of bridge will change to 0 according to PCIe r5.0, sec However,
> the pci_dev->ltr_path value of bridge is still 1.
> For following conditions, check and re-configure "LTR Mechanism Enable" bit
> of bridge to make "LTR Mechanism Enable" bit match ltr_path value.
>    -before configuring device's LTR for hot-remove/hot-add
>    -before restoring device's DEVCTL2 register when restore device state
> Signed-off-by: Mingchuang Qiao <mingchuang.qiao at mediatek.com>

Reviewed-by: Mika Westerberg <mika.westerberg at linux.intel.com>

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