[PATCH v2 6/7] KVM: arm64: Upgrade PMU support to ARMv8.4
Marc Zyngier
maz at kernel.org
Wed Feb 3 05:36:59 EST 2021
Hi Eric,
On 2021-01-27 17:53, Auger Eric wrote:
> Hi Marc,
>
> On 1/25/21 1:26 PM, Marc Zyngier wrote:
>> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be
>> pretty easy. All that is required is support for PMMIR_EL1, which
>> is read-only, and for which returning 0 is a valid option as long
>> as we don't advertise STALL_SLOT as an implemented event.
>>
>> Let's just do that and adjust what we return to the guest.
>>
>> Signed-off-by: Marc Zyngier <maz at kernel.org>
>> ---
>> arch/arm64/include/asm/sysreg.h | 3 +++
>> arch/arm64/kvm/pmu-emul.c | 6 ++++++
>> arch/arm64/kvm/sys_regs.c | 11 +++++++----
>> 3 files changed, 16 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h
>> b/arch/arm64/include/asm/sysreg.h
>> index 8b5e7e5c3cc8..2fb3f386588c 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -846,7 +846,10 @@
>>
>> #define ID_DFR0_PERFMON_SHIFT 24
>>
>> +#define ID_DFR0_PERFMON_8_0 0x3
>> #define ID_DFR0_PERFMON_8_1 0x4
>> +#define ID_DFR0_PERFMON_8_4 0x5
>> +#define ID_DFR0_PERFMON_8_5 0x6
>>
>> #define ID_ISAR4_SWP_FRAC_SHIFT 28
>> #define ID_ISAR4_PSR_M_SHIFT 24
>> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
>> index 398f6df1bbe4..72cd704a8368 100644
>> --- a/arch/arm64/kvm/pmu-emul.c
>> +++ b/arch/arm64/kvm/pmu-emul.c
>> @@ -795,6 +795,12 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu,
>> bool pmceid1)
>> base = 0;
>> } else {
>> val = read_sysreg(pmceid1_el0);
>> + /*
>> + * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled
>> + * as RAZ
>> + */
>> + if (vcpu->kvm->arch.pmuver >= ID_AA64DFR0_PMUVER_8_4)
>> + val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32);
> what about the STALL_SLOT_BACKEND and FRONTEND events then?
Aren't these a mandatory ARMv8.1 feature? I don't see a reason to
drop them.
>> base = 32;
>> }
>>
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 8f79ec1fffa7..5da536ab738d 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1051,16 +1051,16 @@ static u64 read_id_reg(const struct kvm_vcpu
>> *vcpu,
>> /* Limit debug to ARMv8.0 */
>> val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
>> val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
>> - /* Limit guests to PMUv3 for ARMv8.1 */
>> + /* Limit guests to PMUv3 for ARMv8.4 */
>> val = cpuid_feature_cap_perfmon_field(val,
>> ID_AA64DFR0_PMUVER_SHIFT,
>> - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0);
>> + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
>> break;
>> case SYS_ID_DFR0_EL1:
>> - /* Limit guests to PMUv3 for ARMv8.1 */
>> + /* Limit guests to PMUv3 for ARMv8.4 */
>> val = cpuid_feature_cap_perfmon_field(val,
>> ID_DFR0_PERFMON_SHIFT,
>> - kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0);
>> + kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
>> break;
>> }
>>
>> @@ -1496,6 +1496,7 @@ static const struct sys_reg_desc sys_reg_descs[]
>> = {
>>
>> { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown,
>> PMINTENSET_EL1 },
>> { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown,
>> PMINTENSET_EL1 },
> "KVM: arm64: Hide PMU registers from userspace when not available"
> changed the above, doesn't it?
Yes, that's because the fix didn't make it in mainline before
5.11-rc5, and I based this on -rc4. I'll fix it at merge time.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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