[PATCH] ARM: kexec: Fix panic after TLB are invalidated
giancarlo.ferrari89 at gmail.com
Mon Feb 1 05:10:43 EST 2021
On Tue, Jan 12, 2021 at 04:49:06PM +0000, Giancarlo Ferrari wrote:
> machine_kexec() need to set rw permission in text and rodata sections
> to assign some variables (e.g. kexec_start_address). To do that at
> the end (after flushing pdm in memory, inv D-Cache, etc.) it needs to
> invalidate TLB [section] entries.
> If during the TLB invalidation an interrupt occours, which might cause
> a context switch, there is the risk to inject invalid TLBs, with ro
> When trying to assign .text labels, this lead to the following issue:
> "Unable to handle kernel paging request at virtual address <valid_addr>"
> with FSR 0x80d.
> Signed-off-by: Giancarlo Ferrari <giancarlo.ferrari89 at gmail.com>
> arch/arm/kernel/machine_kexec.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
has been re-submitted here:
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