[PATCH 5/7] arm64: dts: marvell: Remove unused num-viewport from pcie node

[Jisheng Zhang]

After commit 281f1f99cf3a("PCI: dwc: Detect number of iATU windows"),
the number of iATU windows is detected at runtime, what's more,
the 'num-viewport' property parsing has been removed, so remove the
unused num-viewport from pcie nodes.

Signed-off-by: Jisheng Zhang <jszhang at kernel.org>
---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi      | 1 -
 arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts | 1 -
 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts            | 1 -
 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts            | 1 -
 arch/arm64/boot/dts/marvell/cn9130-db.dtsi              | 1 -
 arch/arm64/boot/dts/marvell/cn9131-db.dtsi              | 1 -
 arch/arm64/boot/dts/marvell/cn9132-db.dtsi              | 2 --
 7 files changed, 8 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index adbfecc678b5..860912e47732 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -180,7 +180,6 @@ &cp0_pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&cp0_pcie_pins>;
 	num-lanes = <4>;
-	num-viewport = <8>;
 	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
 	ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
 	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
index dac85fa748de..c5ba03c2194d 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
@@ -330,7 +330,6 @@ &cp0_pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&cp0_pcie_pins>;
 	num-lanes = <1>;
-	num-viewport = <8>;
 	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
 	ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
 	phys = <&cp0_comphy0 0>;
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
index a7b6dfba8af5..ccb48d81604a 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
@@ -12,7 +12,6 @@ / {
 &cp0_pcie0 {
 	status = "okay";
 	num-lanes = <4>;
-	num-viewport = <8>;
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp0_comphy0 0
 		&cp0_comphy1 0
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
index 0904cb0309ae..4c68c8c310ae 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
@@ -12,7 +12,6 @@ / {
 &cp0_pcie0 {
 	status = "okay";
 	num-lanes = <1>;
-	num-viewport = <8>;
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp0_comphy0 0>;
 	iommu-map =
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
index c00b69b88bd2..54f40674808b 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -271,7 +271,6 @@ partition at 1000000 {
 &cp0_pcie0 {
 	status = "okay";
 	num-lanes = <4>;
-	num-viewport = <8>;
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp0_comphy0 0
 		&cp0_comphy1 0
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
index f995b1bcda01..ccf162fa751b 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
@@ -112,7 +112,6 @@ &cp1_pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&cp1_pcie_reset_pins>;
 	num-lanes = <2>;
-	num-viewport = <8>;
 	marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 	/* Generic PHY, providing serdes lanes */
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
index 3f1795fb4fe7..be96d5f3398e 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
@@ -153,7 +153,6 @@ cp2_module_expander1: pca9555 at 21 {
 &cp2_pcie0 {
 	status = "okay";
 	num-lanes = <2>;
-	num-viewport = <8>;
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp2_comphy0 0
 		&cp2_comphy1 0>;
@@ -163,7 +162,6 @@ &cp2_pcie0 {
 &cp2_pcie2 {
 	status = "okay";
 	num-lanes = <1>;
-	num-viewport = <8>;
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp2_comphy5 2>;
 };
-- 
2.34.1