[PATCH 3/3] tty: serial: meson: add UART driver compatible with S4 SoC on-chip

[Martin Blumenstingl]

Hello,

On Mon, Dec 27, 2021 at 7:56 AM Yu Tu <yu.tu at amlogic.com> wrote:
[...]
> > Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL?
> > If there's still a 24MHz XTAL then I think this description is not
> > correct - at least based on how I understand the UART controller.
> >
> The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode).
> This register description is the same as the G12A and G12B you know.
Thank you for this explanation!
So the problem is that we're not touching bit 26 and bit 27 - and with
the updated romcode you would not get any serial output since the
divider is calculated off the wrong clock.

I agree with Jerome that we shouldn't put a flag in device-tree.

Also I did some experimenting with Jerome's idea to implement the
clocks using CCF (common clock framework), see the attached patches.
It was a bit tricky because some initial clean-ups were needed in the
serial driver.
Note: I have only briefly tested this on a 32-bit Meson8m2 SoC, see my
attached patches and the clk_summary debugfs output.
In fact, I expect that there are some issues with at least one of the
patches as the whole bit 26 and bit 27 code is untested.

Do you see any problems with this patch?
Could you try to implement CCF support with the idea from the attached
patches (you don't need to re-use them, I just wrote them to make it
clearer in our discussion what we're talking about).


Best regards,
Martin
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# cat /sys/kernel/debug/clk/clk_summary 
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
[...]
 xtal                                 6        6        2    24000000          0     0  50000         Y
[...]
    c81004c0.serial#xtal_div3         0        0        0     8000000          0     0  50000         Y
[...]
    fixed_pll_dco                     1        1        0  2550000000          0     0  50000         Y
       fixed_pll                      1        1        0  2550000000          0     0  50000         Y
[...]
          fclk_div3_div               1        1        0   850000000          0     0  50000         Y
             fclk_div3                2        2        0   850000000          0     0  50000         Y
[...]
                mpeg_clk_sel          1        1        0   850000000          0     0  50000         Y
                   mpeg_clk_div       1        1        0   141666667          0     0  50000         Y
                      clk81          17       20        0   141666667          0     0  50000         Y
[...]
                         c81004c0.serial#clk81_div4       1        1        0    35416666          0     0  50000         Y
                            c81004c0.serial#use_xtal       1        1        0    35416666          0     0  50000         Y
                               c81004c0.serial#baud_div       1        1        0      115364          0     0  50000         Y
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