[xilinx-xlnx:xlnx_rebase_v5.4 1277/1768] drivers/gpio/gpio-xilinx.c:694:39: sparse: sparse: incorrect type in argument 1 (different base types)
kernel test robot
lkp at intel.com
Fri Dec 17 09:20:36 PST 2021
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v5.4
head: abafefebd1f1e040eef74e4ab571ea08bf745641
commit: af0c19b6f15388c554317280433100fd9f3d7d0a [1277/1768] gpio: xilinx: Use xilinx tested gpio driver
config: i386-randconfig-s002-20211216 (https://download.01.org/0day-ci/archive/20211218/202112180150.eRkJwheM-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.4-dirty
# https://github.com/Xilinx/linux-xlnx/commit/af0c19b6f15388c554317280433100fd9f3d7d0a
git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
git fetch --no-tags xilinx-xlnx xlnx_rebase_v5.4
git checkout af0c19b6f15388c554317280433100fd9f3d7d0a
# save the config file to linux build tree
mkdir build_dir
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpio/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/gpio/gpio-xilinx.c:694:39: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __be32 const [usertype] *p @@ got unsigned int const [usertype] *[assigned] tree_info @@
drivers/gpio/gpio-xilinx.c:694:39: sparse: expected restricted __be32 const [usertype] *p
drivers/gpio/gpio-xilinx.c:694:39: sparse: got unsigned int const [usertype] *[assigned] tree_info
vim +694 drivers/gpio/gpio-xilinx.c
586
587 /**
588 * xgpio_of_probe - Probe method for the GPIO device.
589 * @pdev: platform device instance
590 *
591 * This function probes the GPIO device in the device tree. It initializes the
592 * driver data structure.
593 *
594 * Return:
595 * It returns 0, if the driver is bound to the GPIO device, or
596 * a negative value if there is an error.
597 */
598 static int xgpio_of_probe(struct platform_device *pdev)
599 {
600 struct device_node *np = pdev->dev.of_node;
601 struct xgpio_instance *chip, *chip_dual;
602 int status = 0;
603 const u32 *tree_info;
604 u32 ngpio;
605 u32 cells = 2;
606
607 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
608 if (!chip)
609 return -ENOMEM;
610
611 /* Update GPIO state shadow register with default value */
612 of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state);
613
614 /* By default, all pins are inputs */
615 chip->gpio_dir = 0xFFFFFFFF;
616
617 /* Update GPIO direction shadow register with default value */
618 of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir);
619
620 chip->no_init = of_property_read_bool(np, "xlnx,no-init");
621
622 /* Update cells with gpio-cells value */
623 of_property_read_u32(np, "#gpio-cells", &cells);
624
625 /*
626 * Check device node and parent device node for device width
627 * and assume default width of 32
628 */
629 if (of_property_read_u32(np, "xlnx,gpio-width", &ngpio))
630 ngpio = 32;
631 chip->mmchip.gc.ngpio = (u16)ngpio;
632
633 spin_lock_init(&chip->gpio_lock);
634
635 chip->mmchip.gc.parent = &pdev->dev;
636 chip->mmchip.gc.owner = THIS_MODULE;
637 chip->mmchip.gc.of_xlate = xgpio_xlate;
638 chip->mmchip.gc.of_gpio_n_cells = cells;
639 chip->mmchip.gc.direction_input = xgpio_dir_in;
640 chip->mmchip.gc.direction_output = xgpio_dir_out;
641 chip->mmchip.gc.get = xgpio_get;
642 chip->mmchip.gc.set = xgpio_set;
643 chip->mmchip.gc.request = xgpio_request;
644 chip->mmchip.gc.free = xgpio_free;
645 chip->mmchip.gc.set_multiple = xgpio_set_multiple;
646
647 chip->mmchip.save_regs = xgpio_save_regs;
648
649 platform_set_drvdata(pdev, chip);
650
651 chip->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
652 if (IS_ERR(chip->clk)) {
653 if (PTR_ERR(chip->clk) != -ENOENT) {
654 if (PTR_ERR(chip->clk) != -EPROBE_DEFER)
655 dev_err(&pdev->dev, "Input clock not found\n");
656 return PTR_ERR(chip->clk);
657 }
658
659 /*
660 * Clock framework support is optional, continue on
661 * anyways if we don't find a matching clock.
662 */
663 chip->clk = NULL;
664 }
665
666 status = clk_prepare_enable(chip->clk);
667 if (status < 0) {
668 dev_err(&pdev->dev, "Failed to prepare clk\n");
669 return status;
670 }
671
672 pm_runtime_set_active(&pdev->dev);
673 pm_runtime_enable(&pdev->dev);
674
675 /* Call the OF gpio helper to setup and register the GPIO device */
676 status = of_mm_gpiochip_add(np, &chip->mmchip);
677 if (status) {
678 pr_err("%pOF: error in probe function with status %d\n",
679 np, status);
680 goto err_unprepare_clk;
681 }
682
683 status = xgpio_irq_setup(np, chip);
684 if (status) {
685 pr_err("%s: GPIO IRQ initialization failed %d\n",
686 np->full_name, status);
687 goto err_pm_put;
688 }
689
690 pr_info("XGpio: %s: registered, base is %d\n", np->full_name,
691 chip->mmchip.gc.base);
692
693 tree_info = of_get_property(np, "xlnx,is-dual", NULL);
> 694 if (tree_info && be32_to_cpup(tree_info)) {
695 chip_dual = devm_kzalloc(&pdev->dev, sizeof(*chip_dual),
696 GFP_KERNEL);
697 if (!chip_dual)
698 goto err_pm_put;
699
700 /* Add dual channel offset */
701 chip_dual->offset = XGPIO_CHANNEL_OFFSET;
702
703 /* Update GPIO state shadow register with default value */
704 of_property_read_u32(np, "xlnx,dout-default-2",
705 &chip_dual->gpio_state);
706
707 /* By default, all pins are inputs */
708 chip_dual->gpio_dir = 0xFFFFFFFF;
709
710 /* Update GPIO direction shadow register with default value */
711 of_property_read_u32(np, "xlnx,tri-default-2",
712 &chip_dual->gpio_dir);
713
714 /*
715 * Check device node and parent device node for device width
716 * and assume default width of 32
717 */
718 if (of_property_read_u32(np, "xlnx,gpio2-width", &ngpio))
719 ngpio = 32;
720 chip_dual->mmchip.gc.ngpio = (u16)ngpio;
721
722 spin_lock_init(&chip_dual->gpio_lock);
723
724 chip_dual->mmchip.gc.parent = &pdev->dev;
725 chip_dual->mmchip.gc.owner = THIS_MODULE;
726 chip_dual->mmchip.gc.of_xlate = xgpio_xlate;
727 chip_dual->mmchip.gc.of_gpio_n_cells = cells;
728 chip_dual->mmchip.gc.direction_input = xgpio_dir_in;
729 chip_dual->mmchip.gc.direction_output = xgpio_dir_out;
730 chip_dual->mmchip.gc.get = xgpio_get;
731 chip_dual->mmchip.gc.set = xgpio_set;
732 chip_dual->mmchip.gc.request = xgpio_request;
733 chip_dual->mmchip.gc.free = xgpio_free;
734 chip_dual->mmchip.gc.set_multiple = xgpio_set_multiple;
735
736 chip_dual->mmchip.save_regs = xgpio_save_regs;
737
738 chip->mmchip_dual = &chip_dual->mmchip;
739
740 status = xgpio_irq_setup(np, chip_dual);
741 if (status) {
742 pr_err("%s: GPIO IRQ initialization failed %d\n",
743 np->full_name, status);
744 goto err_pm_put;
745 }
746
747 /* Call the OF gpio helper to setup and register the GPIO dev */
748 status = of_mm_gpiochip_add(np, &chip_dual->mmchip);
749 if (status) {
750 pr_err("%s: error in probe function with status %d\n",
751 np->full_name, status);
752 goto err_pm_put;
753 }
754 pr_info("XGpio: %s: dual channel registered, base is %d\n",
755 np->full_name, chip_dual->mmchip.gc.base);
756 }
757
758 pm_runtime_put(&pdev->dev);
759 return 0;
760
761 err_pm_put:
762 pm_runtime_put(&pdev->dev);
763 err_unprepare_clk:
764 pm_runtime_disable(&pdev->dev);
765 clk_disable_unprepare(chip->clk);
766 return status;
767 }
768
---
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