[PATCH 1/3] arm64: dts: mnt-reform2: add internal display support

[Shawn Guo]

On Sun, Dec 12, 2021 at 02:49:10PM +0100, Lucas Stach wrote:
> This adds support for the internal display of the Reform2 Laptop, which
> is connected to the i.MX8MQ via a MIPI-DSI->eDP bridge chip. Clocking
> is derived from a system PLL, which provides quite good rate matching
> for the single supported display mode and keeps the video PLL free for
> usage with the external display, which isn't supported yet.
> 
> Signed-off-by: Lucas Stach <dev at lynxeye.de>
> ---
>  .../boot/dts/freescale/imx8mq-mnt-reform2.dts | 139 ++++++++++++++++++
>  1 file changed, 139 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> index 4f2db6197b39..b96825799f3d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> @@ -13,6 +13,30 @@ / {
>  	model = "MNT Reform 2";
>  	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
>  
> +	backlight: backlight {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_backlight>;
> +		compatible = "pwm-backlight";

Let's start properties with compatible.

> +		pwms = <&pwm2 0 10000>;
> +		power-supply = <&reg_main_usb>;
> +		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> +		brightness-levels = <0 32 64 128 160 200 255>;
> +		default-brightness-level = <6>;
> +	};
> +
> +	panel {
> +		compatible = "innolux,n125hce-gn1", "simple-panel";
> +		power-supply = <&reg_main_3v3>;
> +		backlight = <&backlight>;
> +		no-hpd;
> +
> +		port {
> +			panel_in: endpoint {
> +				remote-endpoint = <&edp_bridge_out>;
> +			};
> +		};
> +	};
> +
>  	pcie1_refclk: clock-pcie1-refclk {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> @@ -41,6 +65,22 @@ reg_main_usb: regulator-main-usb {
>  		vin-supply = <&reg_main_5v>;
>  	};
>  
> +	reg_main_1v8: regulator-main-1v8 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "1V8";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +		vin-supply = <&reg_main_3v3>;
> +	};
> +
> +	reg_main_1v2: regulator-main-1v2 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "1V2";
> +		regulator-min-microvolt = <1200000>;
> +		regulator-max-microvolt = <1200000>;
> +		vin-supply = <&reg_main_5v>;
> +	};
> +
>  	sound {
>  		compatible = "fsl,imx-audio-wm8960";
>  		audio-cpu = <&sai2>;
> @@ -60,6 +100,13 @@ sound {
>  	};
>  };
>  
> +&dphy {
> +	status = "okay";

Let's end properties with status.

> +	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
> +	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
> +	assigned-clock-rates = <25000000>;
> +};
> +
>  &fec1 {
>  	status = "okay";
>  };
> @@ -83,6 +130,66 @@ rtc at 68 {
>  	};
>  };
>  
> +&i2c4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c4>;
> +	status = "okay";
> +
> +	edp_bridge: bridge at 2c {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_edp_bridge>;
> +		compatible = "ti,sn65dsi86";

Same here.

> +		reg = <0x2c>;
> +		enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
> +		vccio-supply = <&reg_main_1v8>;
> +		vpll-supply = <&reg_main_1v8>;
> +		vcca-supply = <&reg_main_1v2>;
> +		vcc-supply = <&reg_main_1v2>;
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port at 0 {
> +				reg = <0>;
> +
> +				edp_bridge_in: endpoint {
> +					remote-endpoint = <&mipi_dsi_out>;
> +				};
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +
> +				edp_bridge_out: endpoint {
> +					remote-endpoint = <&panel_in>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&lcdif {
> +	status = "okay";

Same here.

Shawn

> +	assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
> +	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
> +	/delete-property/assigned-clock-rates;
> +};
> +
> +&mipi_dsi {
> +	status = "okay";
> +
> +	ports {
> +		port at 1 {
> +			reg = <1>;
> +
> +			mipi_dsi_out: endpoint {
> +				remote-endpoint = <&edp_bridge_in>;
> +			};
> +		};
> +	};
> +};
> +
>  &pcie1 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie1>;
> @@ -95,6 +202,13 @@ &pcie1 {
>  	status = "okay";
>  };
>  
> +&pwm2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm2>;
> +	status = "okay";
> +};
> +
> +
>  &reg_1p8v {
>  	vin-supply = <&reg_main_5v>;
>  };
> @@ -168,6 +282,18 @@ &usdhc2 {
>  };
>  
>  &iomuxc {
> +	pinctrl_backlight: backlightgrp {
> +		fsl,pins = <
> +			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x3
> +		>;
> +	};
> +
> +	pinctrl_edp_bridge: edpbridgegrp {
> +		fsl,pins = <
> +			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x1
> +		>;
> +	};
> +
>  	pinctrl_i2c3: i2c3grp {
>  		fsl,pins = <
>  			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
> @@ -175,12 +301,25 @@ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
>  		>;
>  	};
>  
> +	pinctrl_i2c4: i2c4grp {
> +		fsl,pins = <
> +			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022
> +			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000022
> +		>;
> +	};
> +
>  	pinctrl_pcie1: pcie1grp {
>  		fsl,pins = <
>  			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
>  		>;
>  	};
>  
> +	pinctrl_pwm2: pwm2grp {
> +		fsl,pins = <
> +			MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT			0x3
> +		>;
> +	};
> +
>  	pinctrl_sai2: sai2grp {
>  		fsl,pins = <
>  			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
> -- 
> 2.31.1
>